JPS6195114U - - Google Patents
Info
- Publication number
- JPS6195114U JPS6195114U JP17875384U JP17875384U JPS6195114U JP S6195114 U JPS6195114 U JP S6195114U JP 17875384 U JP17875384 U JP 17875384U JP 17875384 U JP17875384 U JP 17875384U JP S6195114 U JPS6195114 U JP S6195114U
- Authority
- JP
- Japan
- Prior art keywords
- input
- audio signal
- fet
- amplifier circuit
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005236 sound signal Effects 0.000 claims 7
- 239000003990 capacitor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Description
第１図は本考案の一実施例の構成を示す回路図
、第２図は従来のプリアンプ装置の構成を示す回
路図である。
１，５……増幅回路、２，３，６，７……セレ
クタ、４，８……スイツチ、Ｒ１〜Ｒ９……抵抗
、Ｑ１〜Ｑ５……ＦＥＴ、Ｄ１〜Ｄ４……ダイオ
ード。
FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a circuit diagram showing the configuration of a conventional preamplifier device. 1, 5...Amplifier circuit, 2,3,6,7...Selector, 4,8...Switch, R1 to R9 ...Resistor, Q1 to Q5 ...FET, D1 to D4 ... …diode.
Claims (1)
レベルの高い第２の音声信号と、周波数補償を必
要とする第３の音声信号とが選択的に一方の入力
にされかつ他方の入力がアースされた増幅回路と
、この増幅回路の一方の出力から前記他方の入力
への帰還ラインに順に直列に介挿された第１およ
び第２の抵抗と、前記帰還ラインの前記第１およ
び第２の抵抗間にドレインおよびソース端子が接
続された第１のＦＥＴと、前記第１の抵抗の両端
にドレインおよびソース端子が接続された第２の
ＦＥＴと、前記第１の抵抗の前記第１のＦＥＴ側
の一端から前記増幅回路の他方の入力間に直列に
介挿された第３の抵抗およびコンデンサと、前記
増幅回路の前記他方の入力とアース間に接続され
た第４の抵抗と、前記第１の音声信号が前記増幅
回路の前記一方の入力として選択されたとき前記
第１のＦＥＴのゲートのみに電圧を印加し、前記
第２の音声信号が前記一方の入力として選択され
たときには前記第１および第２のＦＥＴのゲート
に電圧を印加し、前記第３の音声信号が選択され
たときには前記第２のＦＥＴのゲートのみに電圧
を印加するような切換動作をするセレクタと、こ
のセレクタにより前記第２のＦＥＴのゲートのみ
に電圧が印加されているとき選択的にこのゲート
電圧をアースにバイパスさせるような切換動作を
するスイツチとからなることを特徴とするプリア
ンプ装置。 A first audio signal, a second audio signal having a higher level than the first audio signal, and a third audio signal requiring frequency compensation are selectively inputted to one input and inputted to the other input. an amplifier circuit which is grounded; first and second resistors inserted in series in order in a feedback line from one output of the amplifier circuit to the other input; and the first and second resistors of the feedback line. a first FET whose drain and source terminals are connected between two resistors; a second FET whose drain and source terminals are connected to both ends of the first resistor; a third resistor and a capacitor inserted in series between one end of the FET side and the other input of the amplifier circuit, and a fourth resistor connected between the other input of the amplifier circuit and ground; When the first audio signal is selected as the one input of the amplifier circuit, a voltage is applied only to the gate of the first FET, and when the second audio signal is selected as the one input, a selector that performs a switching operation such that voltage is applied to the gates of the first and second FETs, and voltage is applied only to the gate of the second FET when the third audio signal is selected; A preamplifier device comprising: a switch that selectively performs a switching operation to bypass the gate voltage to ground when voltage is applied only to the gate of the second FET by a selector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17875384U JPS6195114U (en) | 1984-11-27 | 1984-11-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17875384U JPS6195114U (en) | 1984-11-27 | 1984-11-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6195114U true JPS6195114U (en) | 1986-06-19 |
Family
ID=30736320
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17875384U Pending JPS6195114U (en) | 1984-11-27 | 1984-11-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6195114U (en) |
-
1984
- 1984-11-27 JP JP17875384U patent/JPS6195114U/ja active Pending
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