JPS62135231U - - Google Patents
Info
- Publication number
- JPS62135231U JPS62135231U JP2378886U JP2378886U JPS62135231U JP S62135231 U JPS62135231 U JP S62135231U JP 2378886 U JP2378886 U JP 2378886U JP 2378886 U JP2378886 U JP 2378886U JP S62135231 U JPS62135231 U JP S62135231U
- Authority
- JP
- Japan
- Prior art keywords
- mos
- fet
- resistors
- drain
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 9
Landscapes
- Electronic Switches (AREA)
Description
第1図は本考案にかかるスイツチ回路の一実施
例の構成図、第2図は第1図の等価回路図、第3
図は第2図の等価回路図、第4図は第3図の等価
回路図、第5図〜第8図は動作説明用のタイムチ
ヤート、第9図及び第10図は本考案にかかるス
イツチ回路の他の構成例を示した図、第11図は
スイツチ回路の従来例の構成図、第12図は第1
1図の等価回路図である。
1……制御端子、11……一端、12……他端
、Q1……第1のMOS FET、Q2……第2
のMOS FET、Q3……第3のMOS FE
T、Q4……第4のMOS FET、R1〜R3
……抵抗。
Figure 1 is a block diagram of an embodiment of a switch circuit according to the present invention, Figure 2 is an equivalent circuit diagram of Figure 1, and Figure 3 is an equivalent circuit diagram of Figure 1.
The figure is an equivalent circuit diagram of Figure 2, Figure 4 is an equivalent circuit diagram of Figure 3, Figures 5 to 8 are time charts for explaining operation, and Figures 9 and 10 are switches according to the present invention. Diagrams showing other configuration examples of the circuit, FIG. 11 is a configuration diagram of a conventional example of a switch circuit, and FIG. 12 is a diagram of a conventional switch circuit.
FIG. 1 is an equivalent circuit diagram of FIG. 1... Control terminal, 1 1 ... One end, 1 2 ... Other end, Q1... First MOS FET, Q2... Second
MOS FET, Q3...Third MOS FE
T, Q4...Fourth MOS FET, R1 to R3
……resistance.
Claims (1)
ETと、 ドレインから出力が取出される第2のMOS
FETと、 前記第1及び第2のMOS FETのソースと
ソースの間に直列接続された複数の抵抗と、 ソースは前記抵抗どうしの接続点に、ゲートは
前記第1のMOS FETのソースに、ドレイン
は前記第1のMOS FETゲートに夫々接続さ
れている第3のMOS FETと、 ソースは前記抵抗どうしの接続点に、ゲートは
前記第2のMOS FETのソースに、ドレイン
は前記第2のMOS FETのゲートに夫々接続
されている第4のMOS FETと、 一端には前記第1及び第2のMOS FETの
ゲートが接続され、他端には前記抵抗どうしの接
続点が夫々接続され、両端間には制御電圧が印加
される制御端子と、 この制御端子の両端間に接続されたシヤント抵
抗、 を具備したことを特徴とするスイツチ回路。[Claims for Utility Model Registration] In a switch circuit using transistors, the first MOS F to which an input is given to the drain
ET and a second MOS whose output is taken from the drain
FET, a plurality of resistors connected in series between the sources of the first and second MOS FETs, the source being connected to the connection point between the resistors, and the gate being connected to the source of the first MOS FET, A third MOS FET has a drain connected to the first MOS FET gate, a source to the connection point between the resistors, a gate to the source of the second MOS FET, and a drain to the second MOS FET. a fourth MOS FET connected to the gates of the MOS FETs, one end connected to the gates of the first and second MOS FETs, and the other end connected to the connection points of the resistors, respectively; A switch circuit comprising: a control terminal to which a control voltage is applied; and a shunt resistor connected between both ends of the control terminal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2378886U JPS62135231U (en) | 1986-02-20 | 1986-02-20 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2378886U JPS62135231U (en) | 1986-02-20 | 1986-02-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62135231U true JPS62135231U (en) | 1987-08-26 |
Family
ID=30822409
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2378886U Pending JPS62135231U (en) | 1986-02-20 | 1986-02-20 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62135231U (en) |
-
1986
- 1986-02-20 JP JP2378886U patent/JPS62135231U/ja active Pending