JPS62201516U - - Google Patents
Info
- Publication number
- JPS62201516U JPS62201516U JP8890186U JP8890186U JPS62201516U JP S62201516 U JPS62201516 U JP S62201516U JP 8890186 U JP8890186 U JP 8890186U JP 8890186 U JP8890186 U JP 8890186U JP S62201516 U JPS62201516 U JP S62201516U
- Authority
- JP
- Japan
- Prior art keywords
- fet
- fade
- output terminal
- changing
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
第１図及び第２図は夫々本考案回路の一実施例
の回路図及びその信号波形図、第３図及び第４図
は夫々従来回路の一例の回路図及びその信号波形
図である。
１ａ，１ｂ……入力端子、２……スイツチ、３
ａ，３ｂ……出力端子、５１，５２……ＦＥＴ、
Ｒ１，Ｒ２……直列抵抗。
1 and 2 are a circuit diagram and a signal waveform diagram of an embodiment of the circuit of the present invention, respectively, and FIGS. 3 and 4 are a circuit diagram and a signal waveform diagram of an example of a conventional circuit, respectively. 1a, 1b...Input terminal, 2...Switch, 3
a, 3b...Output terminal, 5 1 , 5 2 ...FET,
R1 , R2 ...Series resistance.
Claims (1)
続し、ゲート電圧の変化によつて該ＦＥＴの実効
抵抗を制御することにより入力信号をフエードイ
ン／アウトするフエードイン／アウト回路におい
て、上記入力端子と上記出力端子との間に夫々異
なるゲート・ソース遮断電圧を有する複数のＦＥ
Ｔを並列に接続し、各ＦＥＴの実効抵抗を一のゲ
ート電圧の変化によつて制御して入力信号をフエ
ードイン／アウトするよう構成してなるフエード
イン／アウト回路。 In a fade in/out circuit, an FET is connected in parallel between an input terminal and an output terminal, and the input signal is faded in/out by controlling the effective resistance of the FET by changing the gate voltage. A plurality of FEs each having a different gate/source cutoff voltage between the output terminal and the above output terminal.
A fade-in/out circuit configured to connect FETs in parallel and control the effective resistance of each FET by changing a gate voltage to fade in/out an input signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8890186U JPS62201516U (en) | 1986-06-11 | 1986-06-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8890186U JPS62201516U (en) | 1986-06-11 | 1986-06-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62201516U true JPS62201516U (en) | 1987-12-22 |
Family
ID=30947405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8890186U Pending JPS62201516U (en) | 1986-06-11 | 1986-06-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62201516U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5343070U (en) * | 1976-09-16 | 1978-04-13 |
-
1986
- 1986-06-11 JP JP8890186U patent/JPS62201516U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5343070U (en) * | 1976-09-16 | 1978-04-13 |