JPS6437119U - - Google Patents
Info
- Publication number
- JPS6437119U JPS6437119U JP13138887U JP13138887U JPS6437119U JP S6437119 U JPS6437119 U JP S6437119U JP 13138887 U JP13138887 U JP 13138887U JP 13138887 U JP13138887 U JP 13138887U JP S6437119 U JPS6437119 U JP S6437119U
- Authority
- JP
- Japan
- Prior art keywords
- fet
- drain
- resistor
- amplifier
- voltage dividing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Amplifiers (AREA)
Description
第１図は本考案の一実施例の回路図、第２図は
本考案の他の実施例の回路図、第３図は従来の回
路図である。
１，２……ＦＥＴ、１Ｇ，２Ｇ……ゲート端子
、１Ｄ，２Ｄ……ドレイン端子、３，３Ａ，３Ｂ
……ＤＣ増幅器、３ＯＵＴ……ゲートバイアス電
圧出力端子、４，５，６，７……分圧用抵抗器、
８，８Ａ，８Ｂ……ドレイン抵抗器。
FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a circuit diagram of another embodiment of the present invention, and FIG. 3 is a conventional circuit diagram. 1, 2...FET, 1G, 2G...gate terminal, 1D, 2D...drain terminal, 3, 3A, 3B
...DC amplifier, 3OUT...gate bias voltage output terminal, 4,5,6,7...voltage dividing resistor,
8, 8A, 8B...Drain resistor.
Claims (1)
と電源端子間に接続したドレイン抵抗器と、この
ドレイン抵抗器の両端の電圧変動を検出しかつそ
の変動に対応するゲートバイアス電圧を出力する
１つのＤＣ増幅器と、このＤＣ増幅器の出力を分
圧して前記各ＦＥＴのゲート端子に加えるように
各ＦＥＴに夫々設けた分圧抵抗とで構成し、この
分圧抵抗は各ＦＥＴで夫々適切なゲートバイアス
が印加されるように抵抗値を独立して設定したこ
とを特徴とする多段形増幅器用バイアス回路。 A drain resistor is connected between each drain of a plurality of FETs configured in multiple stages and a power supply terminal, and a single drain resistor that detects voltage fluctuations across the drain resistor and outputs a gate bias voltage corresponding to the fluctuation. It consists of a DC amplifier and a voltage dividing resistor provided for each FET so as to divide the output of the DC amplifier and apply it to the gate terminal of each FET, and the voltage dividing resistor is set to an appropriate gate bias for each FET. A bias circuit for a multi-stage amplifier, characterized in that resistance values are independently set so that .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13138887U JPS6437119U (en) | 1987-08-31 | 1987-08-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13138887U JPS6437119U (en) | 1987-08-31 | 1987-08-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6437119U true JPS6437119U (en) | 1989-03-06 |
Family
ID=31387407
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13138887U Pending JPS6437119U (en) | 1987-08-31 | 1987-08-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6437119U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04129408A (en) * | 1990-09-20 | 1992-04-30 | Toshiba Corp | Microwave power amplifier |
| JP2012244559A (en) * | 2011-05-24 | 2012-12-10 | Nec Corp | Power amplifier device with bias circuit |
-
1987
- 1987-08-31 JP JP13138887U patent/JPS6437119U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04129408A (en) * | 1990-09-20 | 1992-04-30 | Toshiba Corp | Microwave power amplifier |
| JP2012244559A (en) * | 2011-05-24 | 2012-12-10 | Nec Corp | Power amplifier device with bias circuit |