JPS62103328U - - Google Patents
Info
- Publication number
- JPS62103328U JPS62103328U JP19533585U JP19533585U JPS62103328U JP S62103328 U JPS62103328 U JP S62103328U JP 19533585 U JP19533585 U JP 19533585U JP 19533585 U JP19533585 U JP 19533585U JP S62103328 U JPS62103328 U JP S62103328U
- Authority
- JP
- Japan
- Prior art keywords
- mos fets
- switch circuit
- terminals
- series
- resistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 6
Description
第１図は本考案にかかるスイツチ回路の一実施
例の構成図、第２図及び第３図は第１図回路の等
価回路図、第４図及び第５図は第１図回路の動作
説明用のタイムチヤート、第６図は入力波形の一
例を示した図、第７図はスイツチ回路の従来例の
構成図、第８図は第７図回路の等価回路図、第９
図は第７図回路の動作説明用のタイムチヤートで
ある。
Ｑ１，Ｑ２…ＭＯＳ ＦＥＴ、Ｒ１…シヤント
抵抗、Ｒ２，Ｒ３…抵抗、Ｃ１…コンデンサ、１
…第１の端子、２…第２の端子。
Figure 1 is a block diagram of an embodiment of the switch circuit according to the present invention, Figures 2 and 3 are equivalent circuit diagrams of the circuit in Figure 1, and Figures 4 and 5 are explanations of the operation of the circuit in Figure 1. Figure 6 is a diagram showing an example of an input waveform, Figure 7 is a configuration diagram of a conventional switch circuit, Figure 8 is an equivalent circuit diagram of the circuit in Figure 7, and Figure 9 is a diagram showing an example of an input waveform.
This figure is a time chart for explaining the operation of the circuit shown in FIG. Q1, Q2...MOS FET, R1 ...shunt resistance, R2 , R3 ...resistor, C1 ...capacitor, 1
...first terminal, 2...second terminal.
Claims (1)
たスイツチ回路において、 前記２個のＭＯＳ ＦＥＴのゲートが接続され
た第１の端子と、 前記２個のＭＯＳ ＦＥＴのソースとソースの
間に直列接続された抵抗群と、 これらの抵抗どうしの接続点に接続された第２
の端子と、 前記第１及び第２の端子の間にそれぞれ両端が
接続されたシヤント抵抗及びコンデンサ、を具備
し、前記２個のＭＯＳ ＦＥＴのドレインのうち
一方のドレインに入力を与え、他方のドレインか
ら出力を取出すとともに、前記第１及び第２の端
子の間にオン・オフ制御のための制御電圧を印加
することを特徴とするスイツチ回路。[Claims for Utility Model Registration] In a switch circuit configured by connecting two MOS FETs in series, a first terminal to which the gates of the two MOS FETs are connected; A group of resistors connected in series between the sources, and a second resistor connected to the connection point between these resistors.
a shunt resistor and a capacitor, both ends of which are connected between the first and second terminals, respectively, the input is applied to one of the drains of the two MOS FETs, and the A switch circuit characterized in that an output is taken out from the drain and a control voltage for on/off control is applied between the first and second terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19533585U JPH0441632Y2 (en) | 1985-12-19 | 1985-12-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19533585U JPH0441632Y2 (en) | 1985-12-19 | 1985-12-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62103328U true JPS62103328U (en) | 1987-07-01 |
| JPH0441632Y2 JPH0441632Y2 (en) | 1992-09-30 |
Family
ID=31153131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19533585U Expired JPH0441632Y2 (en) | 1985-12-19 | 1985-12-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0441632Y2 (en) |
-
1985
- 1985-12-19 JP JP19533585U patent/JPH0441632Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0441632Y2 (en) | 1992-09-30 |
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