JPH01149131U - - Google Patents
Info
- Publication number
- JPH01149131U JPH01149131U JP4503588U JP4503588U JPH01149131U JP H01149131 U JPH01149131 U JP H01149131U JP 4503588 U JP4503588 U JP 4503588U JP 4503588 U JP4503588 U JP 4503588U JP H01149131 U JPH01149131 U JP H01149131U
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- terminal
- output switch
- switch circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Electronic Switches (AREA)
Description
第１図は本考案の一実施例を示す回路図、第２
図は従来のスイツチ回路の一例を示す回路図であ
る。
１Ａ〜１Ｄ……１入力１出力スイツチ回路、Ｑ
１〜Ｑ３，Ｑ１１〜Ｑ１４……ＦＥＴ、Ｒ１〜Ｒ
３……抵抗、Ｔ１，Ｔ１１，Ｔ１２……入力端子
、Ｔ０１，Ｔ０２，ＴＯ，ＴＯ２……出力端子。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
The figure is a circuit diagram showing an example of a conventional switch circuit. 1A~1D...1 input 1 output switch circuit, Q
1 to Q3 , Q11 to Q14 ...FET, R1 to R
3 ...Resistor, T1 , T11 , T12 ...Input terminal, T01 , T02 , TO, TO2 ...Output terminal.
Claims (1)
と接続し入力端と出力端との間に直列接続された
第１及び第２のトランジスタと、ゲートを抵抗を
介して第２の制御端子と接続し前記第１及び第２
のトランジスタの接続点と接地端子との間に接続
された第３のトランジスタとをそれぞれ備えた第
１〜第４の１入力１出力スイツチ回路と、前記第
１及び第４の１入力１出力スイツチ回路の入力端
を接続する第１の入力端子と、前記第２及び第３
の１入力１出力スイツチ回路の入力端を接続する
第２の入力端子と、前記第１及び第２の１入力１
出力スイツチ回路の出力端を接続する第１の出力
端子と、前記第３及び第４の１入力１出力スイツ
チ回路の出力端を接続する第２の出力端子とを有
することを特徴とするスイツチ回路。 first and second transistors each having a gate connected to a first control terminal via a resistor and connected in series between an input end and an output end; and a gate connected to a second control terminal via a resistor. and the first and second
first to fourth one-input, one-output switch circuits each comprising a third transistor connected between a connection point of the transistor and a ground terminal; and the first and fourth one-input, one-output switch circuits, a first input terminal connecting the input ends of the circuit; and the second and third input terminals.
a second input terminal connecting the input end of the one-input one-output switch circuit;
A switch circuit characterized in that it has a first output terminal that connects the output end of the output switch circuit, and a second output terminal that connects the output ends of the third and fourth one-input one-output switch circuits. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4503588U JPH01149131U (en) | 1988-04-01 | 1988-04-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4503588U JPH01149131U (en) | 1988-04-01 | 1988-04-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01149131U true JPH01149131U (en) | 1989-10-16 |
Family
ID=31271365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4503588U Pending JPH01149131U (en) | 1988-04-01 | 1988-04-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01149131U (en) |
-
1988
- 1988-04-01 JP JP4503588U patent/JPH01149131U/ja active Pending