JPH02113425U - - Google Patents
Info
- Publication number
- JPH02113425U JPH02113425U JP2229189U JP2229189U JPH02113425U JP H02113425 U JPH02113425 U JP H02113425U JP 2229189 U JP2229189 U JP 2229189U JP 2229189 U JP2229189 U JP 2229189U JP H02113425 U JPH02113425 U JP H02113425U
- Authority
- JP
- Japan
- Prior art keywords
- source
- whose
- fet
- common potential
- potential point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Amplifiers (AREA)
- Microwave Amplifiers (AREA)
Description
第１図は本考案の一実施例を示す回路図、第２
図はＦＥＴの特性例図、第３図は従来の回路例図
、第４図は第３図の動作説明図、第５図は従来の
他の回路例図、第６図は第５図の動作説明図であ
る。
１５，２１……ＦＥＴ、１６，１８，２２……
伝送線路、１７，２３……入力端子、１９……出
力端子、２０……電流源、Ｒ７〜Ｒ１０……抵抗
、Ｃ１，Ｃ２……コンデンサ。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure shows an example of FET characteristics, Fig. 3 shows an example of a conventional circuit, Fig. 4 shows an explanation of the operation of Fig. 3, Fig. 5 shows an example of another conventional circuit, and Fig. 6 shows an example of the conventional circuit. It is an operation explanatory diagram. 15, 21...FET, 16, 18, 22...
Transmission line, 17, 23...Input terminal, 19...Output terminal, 20...Current source, R7 to R10 ...Resistor, C1 , C2 ...Capacitor.
Claims (1)
に伝送線路を介して出力端子が接続され、ソース
がコンデンサを介して共通電位点に接続された第
１のＦＥＴと、 ゲートに第２の入力端子が接続され、ソースが
前記第１のＦＥＴのソースに接続されるとともに
コンデンサを介して共通電位点に接続された第２
のＥＦＴと、 一端がこれら第１、第２のＦＥＴのソース接続
点に接続され、他端が共通電位点に接続された電
流源、 とで構成されたことを特徴とする高速増幅回路。[Claims for Utility Model Registration] A first FET whose gate is connected to a first input terminal, whose drain is connected to an output terminal via a transmission line, and whose source is connected to a common potential point via a capacitor. , a second FET whose gate is connected to a second input terminal, whose source is connected to the source of the first FET and to a common potential point via a capacitor.
A high-speed amplifier circuit comprising: an EFT; and a current source, one end of which is connected to the source connection point of the first and second FETs, and the other end of which is connected to a common potential point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2229189U JPH02113425U (en) | 1989-02-28 | 1989-02-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2229189U JPH02113425U (en) | 1989-02-28 | 1989-02-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02113425U true JPH02113425U (en) | 1990-09-11 |
Family
ID=31240271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2229189U Pending JPH02113425U (en) | 1989-02-28 | 1989-02-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02113425U (en) |
-
1989
- 1989-02-28 JP JP2229189U patent/JPH02113425U/ja active Pending
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