JPH0181022U - - Google Patents
Info
- Publication number
- JPH0181022U JPH0181022U JP1987176974U JP17697487U JPH0181022U JP H0181022 U JPH0181022 U JP H0181022U JP 1987176974 U JP1987176974 U JP 1987176974U JP 17697487 U JP17697487 U JP 17697487U JP H0181022 U JPH0181022 U JP H0181022U
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- source
- emitters
- differential
- level shift
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 8
Landscapes
- Amplifiers (AREA)
Description
第1図は増幅素子としてトランジスタを用いた
本考案の一実施例を示す回路図、第2図は増幅素
子としてFETを用いた場合を示す回路図、第3
図及び第4図は従来例を示す回路図、第5図は従
来の入力電位差に対する出力電流の特性図、第6
図は本考案による入力電位差に対する出力電流の
特性図、第7図は第1図におけるレベルシフト回
路の具体的な構成の一例を示す回路図、第8図は
本考案の他の実施例を示す回路図である。
主要部分の符号の説明、Q1,Q2……差動対
トランジスタ、Q3,Q4……バツフアトランジ
スタ、VLS1,VLS2……レベルシフト回路
。
FIG. 1 is a circuit diagram showing an embodiment of the present invention using a transistor as an amplifying element, FIG. 2 is a circuit diagram showing an example of using an FET as an amplifying element, and FIG.
4 and 4 are circuit diagrams showing a conventional example, FIG. 5 is a characteristic diagram of the output current with respect to the conventional input potential difference, and FIG.
The figure is a characteristic diagram of the output current with respect to the input potential difference according to the present invention, FIG. 7 is a circuit diagram showing an example of a specific configuration of the level shift circuit in FIG. 1, and FIG. 8 is a diagram showing another embodiment of the present invention. It is a circuit diagram. Explanation of symbols of main parts: Q 1 , Q 2 . . . differential pair transistors, Q 3 , Q 4 . . . buffer transistors, VLS 1 , VLS 2 . . . level shift circuit.
Claims (1)
介して共通接続されて差動動作をなす第1、第2
のトランジスタを含む差動増幅回路であつて、前
記第1、第2のトランジスタの各コレクタ(又は
ドレイン)に各エミツタ(又はソース)がそれぞ
れ接続されかつ各ベース(又はゲート)が差動入
力端となる第3、第4のトランジスタと、前記第
1、第2のトランジスタの各ベース(又はゲート
)と前記第4、第3のトランジスタのエミツタ(
又はソース)との間に接続されたレベルシフト回
路とを備えたことを特徴とする差動増幅回路。 The first and second emitters (or sources) are commonly connected directly or through a resistor to perform differential operation.
A differential amplifier circuit including a transistor, wherein each emitter (or source) is connected to each collector (or drain) of the first and second transistors, and each base (or gate) is connected to a differential input terminal. , the bases (or gates) of the first and second transistors, and the emitters of the fourth and third transistors (
or a level shift circuit connected between the source and the source.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987176974U JPH0181022U (en) | 1987-11-19 | 1987-11-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987176974U JPH0181022U (en) | 1987-11-19 | 1987-11-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0181022U true JPH0181022U (en) | 1989-05-31 |
Family
ID=31468664
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987176974U Pending JPH0181022U (en) | 1987-11-19 | 1987-11-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0181022U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010034786A (en) * | 2008-07-28 | 2010-02-12 | Yokogawa Electric Corp | Differential amplifier |
-
1987
- 1987-11-19 JP JP1987176974U patent/JPH0181022U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010034786A (en) * | 2008-07-28 | 2010-02-12 | Yokogawa Electric Corp | Differential amplifier |
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