JPS6381518U

JPS6381518U -

Info

Publication number: JPS6381518U
Application number: JP17682686U
Authority: JP
Priority date: 1986-11-17
Filing date: 1986-11-17
Publication date: 1988-05-28

Description

[Brief explanation of the drawing]

第１図及び第２図はそれぞれ本考案の第１及び
第２の実施例の回路図、第３図は従来の２重平衡
差動増幅器の一例の回路図である。Ｂ……バイアス回路、Ｒ_１１，Ｒ_１２，Ｒ_２１，Ｒ_２２……負荷抵抗、Ｑ_１〜Ｑ_７……ＮＰＮト
ランジスタ、Ｑ_１１〜Ｑ_２６……ＭＯＳＦＥＴ、
ＳＩ_１，ＳＩ_２……入力信号、ＳＯ……出力信号
、Ｖ_１１，Ｖ_１２……信号入力端子、ＶＤＤ，Ｖ
ＳＳ……電源端子、ＶＯＵＴ……信号出力端子。 1 and 2 are circuit diagrams of first and second embodiments of the present invention, respectively, and FIG. 3 is a circuit diagram of an example of a conventional double-balanced differential amplifier. B...Bias circuit, R ₁₁ , R ₁₂ , R ₂₁ , _R22 ...Load resistance, _Q1 - _Q7 ...NPN transistor, _Q11 - _Q26 ...MOSFET,
SI ₁ , SI ₂ ... input signal, SO ... output signal, V ₁₁ , V ₁₂ ... signal input terminal, VDD, V
SS...Power supply terminal, VOUT...Signal output terminal.

Claims

[Scope of utility model registration request]

a first MOSFET, and a source of the first MOSFET;
a second MOSFET whose drain is connected to the source of the SFET and whose drain is connected to the signal output terminal; and whose drain is connected to the drain of the first MOSFET and whose gate is connected to the gate of the second MOSFET and the first signal input terminal. Third MOSFE connected
T, the source is connected to the source of the third MOSFET, the drain is connected to the drain of the second MOSFET, and the gate is connected to the first MOSFET.
a fourth MOSFET connected to the gate of T;
a fifth MOSFET having a drain connected to the source of the first MOSFET, a drain connected to the source of the third MOSFET, a source connected to the source of the fifth MOSFET, and a gate having a second signal input; The sixth MO connected to the terminal
SFET, one terminal of which is connected to the first MOSFET.
a first load resistor connected to the drain of the T and whose other terminal is connected to the first power supply terminal; and one terminal connected to the drain of the second MOSFET and whose other terminal is the first power supply terminal. a second load resistor connected to the fifth MOS;
a constant current source connected to the source of the FET and having the other terminal connected to the second power supply terminal; and one terminal connected to the first power supply terminal and the other terminal connected to the second power supply terminal. The first output end is the first output terminal.
a bias circuit connected to the gate of the fifth MOSFET and having a second output terminal connected to the gate of the fifth MOSFET.