JPS62151221U

JPS62151221U -

Info

Publication number: JPS62151221U
Application number: JP3952186U
Authority: JP
Priority date: 1986-03-18
Filing date: 1986-03-18
Publication date: 1987-09-25

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例による温度補償型
高周波増幅器の回路図、第２図は従来の温度補償
型高周波増幅器の回路図、第３図は利得温度特性
図、第４図はゲートバイアス電圧の温度特性図、
第５図はゲートバイアス電圧と利得との関係図、
第６図はこの考案におけるゲートバイアス回路抵
抗とドレイン電流とドレイン電圧の温度特性図で
ある。図において、１はＦＥＴ、２はゲート端子、３
はドレイン端子、９は第１のサーミスタ、１８は
保護抵抗、２０は第２のサーミスタである。なお
、図中、同一符号は同一または相当部分を示す。 Figure 1 is a circuit diagram of a temperature compensated high frequency amplifier according to an embodiment of this invention, Figure 2 is a circuit diagram of a conventional temperature compensated high frequency amplifier, Figure 3 is a gain temperature characteristic diagram, and Figure 4 is a gate bias Voltage temperature characteristic diagram,
Figure 5 is a diagram of the relationship between gate bias voltage and gain.
FIG. 6 is a temperature characteristic diagram of gate bias circuit resistance, drain current, and drain voltage in this invention. In the figure, 1 is FET, 2 is gate terminal, 3
is a drain terminal, 9 is a first thermistor, 18 is a protective resistor, and 20 is a second thermistor. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

a field effect transistor; an input matching circuit connected to a gate terminal of the field effect transistor;
In a high frequency amplifier configured with a gate bias circuit connected to the input matching circuit, an output matching circuit connected to the drain terminal of the field effect transistor, and a drain bias circuit connected to the output matching circuit, the drain bias circuit A temperature compensated high frequency amplifier characterized by being equipped with a gain temperature compensation circuit.