JPS61206329U

JPS61206329U -

Info

Publication number: JPS61206329U
Application number: JP8938386U
Authority: JP
Priority date: 1986-06-13
Filing date: 1986-06-13
Publication date: 1986-12-26

Description

[Brief explanation of the drawing]

第１図及び第２図は従来の定電流制御用論理回
路を示す回路図、第３図はトランジスタの飽和電
圧の非直線性を説明するための特性図、第４図は
本考案の第１の実施例に係る論理回路を示す回路
図、第５図は本考案の第２の実施例に係る論理回
路を示す回路図、及び第６図は本考案の第３の実
施例に係る論理回路を示す回路図である。記号の説明、８：定電流源、９：定電流源端子
、１０：入力端子、１１：出力端子、２１：第１
のトランジスタ、２２：第２のトランジスタ、２
３：第３のトランジスタ、２５，２６：抵抗、３
０：第４のトランジスタ、３５：第５のトランジ
スタ、３６：第６のトランジスタ、４２，４３：
抵抗。 1 and 2 are circuit diagrams showing conventional constant current control logic circuits, FIG. 3 is a characteristic diagram for explaining the nonlinearity of the saturation voltage of a transistor, and FIG. 4 is a circuit diagram showing a conventional constant current control logic circuit. FIG. 5 is a circuit diagram showing a logic circuit according to the second embodiment of the present invention, and FIG. 6 is a circuit diagram showing a logic circuit according to the third embodiment of the present invention. FIG. Explanation of symbols, 8: Constant current source, 9: Constant current source terminal, 10: Input terminal, 11: Output terminal, 21: First
transistor, 22: second transistor, 2
3: Third transistor, 25, 26: Resistor, 3
0: fourth transistor, 35: fifth transistor, 36: sixth transistor, 42, 43:
resistance.

Claims

[Scope of utility model registration request]

A constant current source terminal to be connected to a constant current source, an input terminal for receiving an input signal, an output terminal for sending out an output signal, an electrode terminal to be grounded, and a base connected in common, a first transistor and a second transistor forming a current mirror circuit, the collector of the first transistor being connected to the constant current source terminal, and the collector of the second transistor being connected to the output terminal. a third transistor having an emitter and a base connected to the electrode terminal and the input terminal, respectively, and a collector electrically coupled to the emitter of the second transistor; a fourth transistor whose emitter is connected to the emitter of the first transistor, and whose collector is electrically coupled to the emitter of the first transistor, wherein the first to fourth transistors are all of the same conductivity type; A logic circuit characterized in that the transistor No. 3 performs switching according to an input signal applied to its base.