JPH0390131U

JPH0390131U -

Info

Publication number: JPH0390131U
Application number: JP14963689U
Authority: JP
Priority date: 1989-12-25
Filing date: 1989-12-25
Publication date: 1991-09-13

Description

[Brief explanation of drawings]

第１図は本考案の一実施例の電気回路図、第２
図は第１図の使用例を示す電気回路図、第３図は
入力電圧と出力電圧の波形図、第４図は従来回路
の電気回路図である。Ｑ４……第１のトランジスタ、Ｑ５……第２の
トランジスタ、ＲＬ……負荷抵抗。 Fig. 1 is an electrical circuit diagram of one embodiment of the present invention;
FIG. 3 is an electric circuit diagram showing an example of the use of FIG. 1, FIG. 3 is a waveform diagram of input voltage and output voltage, and FIG. 4 is an electric circuit diagram of a conventional circuit. Q4...first transistor, Q5...second transistor, RL...load resistance.

Claims

[Scope of utility model registration request]

In a self-holding circuit that turns on multiple transistors according to the rising or falling edge of an input pulse and maintains the on state regardless of the presence or absence of pulse input, the emitter is a DC power source and the base is a pulse input terminal. a PNP type first transistor, whose base and collector were respectively connected to the collector and base of the first transistor, and whose emitter was connected to the output terminal and to ground through a load resistor, respectively. A self-holding circuit comprising a second transistor.