JPS63174727U - - Google Patents
Info
- Publication number
- JPS63174727U JPS63174727U JP19803186U JP19803186U JPS63174727U JP S63174727 U JPS63174727 U JP S63174727U JP 19803186 U JP19803186 U JP 19803186U JP 19803186 U JP19803186 U JP 19803186U JP S63174727 U JPS63174727 U JP S63174727U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- resistor
- chener
- diode
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000009977 dual effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Power Sources (AREA)
- Electronic Switches (AREA)
Description
第１図は本考案の一実施例を示す基本電気回路
図、第２図は第１図に示す電気回路の電源投入時
における出力波形図、第３図は従来例の基本電気
回路図、第４図は第３図に示す電気回路の電源投
入時における出力波形図である。
符号、１：第３の抵抗、３：チエナーダイオー
ド、４：第１の抵抗、６：トランジスタ、７：第
２の抵抗。
Fig. 1 is a basic electrical circuit diagram showing an embodiment of the present invention, Fig. 2 is an output waveform diagram of the electrical circuit shown in Fig. 1 when the power is turned on, and Fig. 3 is a basic electrical circuit diagram of a conventional example. FIG. 4 is an output waveform diagram when the electric circuit shown in FIG. 3 is powered on. Symbols, 1: third resistor, 3: Chener diode, 4: first resistor, 6: transistor, 7: second resistor.
Claims (1)
一端を接続し、その接続点をＮＰＮ型トランジス
タのベースに直接接続すると共に、前記トランジ
スタのコレクタと前記チエナーダイオードのカソ
ードとを第２の抵抗を介して接続し、前記トラン
ジスタのエミツタと前記第１の抵抗の他端とを直
流電源のグランド側に接続すると共に前記チエナ
ーダイオードのカソードを直流電源のグランド側
でない側に第３の抵抗を介して接続し、 前記トランジスタのエミツタとコレクタ間でリ
セツト信号を出力すると共に前記トランジスタの
エミツタと前記チエナーダイオードのアノードと
の間で定電圧電源を出力する定電圧電源回路兼用
リセツト回路。[Claims for Utility Model Registration] The anode of the Chener diode and one end of the first resistor are connected, the connection point is directly connected to the base of the NPN transistor, and the collector of the transistor and the cathode of the Chener diode are connected directly to the base of the NPN transistor. are connected through a second resistor, the emitter of the transistor and the other end of the first resistor are connected to the ground side of the DC power supply, and the cathode of the Chener diode is connected to the side other than the ground side of the DC power supply. a constant voltage power supply circuit connected to via a third resistor, outputting a reset signal between the emitter and collector of the transistor, and outputting a constant voltage power supply between the emitter of the transistor and the anode of the Chener diode; Dual purpose reset circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19803186U JPS63174727U (en) | 1986-12-22 | 1986-12-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19803186U JPS63174727U (en) | 1986-12-22 | 1986-12-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63174727U true JPS63174727U (en) | 1988-11-14 |
Family
ID=31158344
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19803186U Pending JPS63174727U (en) | 1986-12-22 | 1986-12-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63174727U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111989639A (en) * | 2018-08-28 | 2020-11-24 | 谷歌有限责任公司 | System and method for communicating a reset via a power line |
-
1986
- 1986-12-22 JP JP19803186U patent/JPS63174727U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111989639A (en) * | 2018-08-28 | 2020-11-24 | 谷歌有限责任公司 | System and method for communicating a reset via a power line |
| JP2021528031A (en) * | 2018-08-28 | 2021-10-14 | グーグル エルエルシーＧｏｏｇｌｅ ＬＬＣ | Systems and methods for sending resets over power lines |