JPS63144730U - - Google Patents
Info
- Publication number
- JPS63144730U JPS63144730U JP17267586U JP17267586U JPS63144730U JP S63144730 U JPS63144730 U JP S63144730U JP 17267586 U JP17267586 U JP 17267586U JP 17267586 U JP17267586 U JP 17267586U JP S63144730 U JPS63144730 U JP S63144730U
- Authority
- JP
- Japan
- Prior art keywords
- pair
- connection point
- collectors
- emitters
- pulse generator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図はこの考案の一実施例を示す回路図、第
２図は第１図の入力端子間及び出力端子間の各電
圧を示す波形図、第３図は従来のトリガパルス発
生装置を示す回路図、第４図は第３図の各端子間
の電圧を示す波形図である。
１，Ｇ…入力端子、ａ，ｂ…出力端子、Ｒ３…
出力抵抗器、Ｑ１，Ｑ２…一対のトランジスタ、
Ｄ３，Ｄ４…ダイオード（抵抗回路）、Ａ…エミ
ツタ同士の接続点、Ｂ…コレクタ同士の接続点、
＋Ｖ…直流電源。尚、図中、同一符号は同一又は
相当部分を示す。
Fig. 1 is a circuit diagram showing an embodiment of this invention, Fig. 2 is a waveform diagram showing each voltage between the input terminals and output terminals of Fig. 1, and Fig. 3 shows a conventional trigger pulse generator. The circuit diagram and FIG. 4 are waveform diagrams showing voltages between the respective terminals in FIG. 3. 1, G...Input terminal, a, b...Output terminal, R3...
Output resistor, Q1, Q2...a pair of transistors,
D3, D4...Diode (resistance circuit), A...Connection point between emitters, B...Connection point between collectors,
+V…DC power supply. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
ぞれのベースが接続され且つ各エミツタ同士及び
各コレクタ同士が接続された一対のエミツタ接地
形のトランジスタと、これらトランジスタの各ベ
ース、エミツタ間に挿入された一対の抵抗回路と
、前記コレクタ同士の接続点及び前記エミツタ同
士の接続点にそれぞれ接続された一対の出力端子
と、直流電源と前記コレクタ同士の接続点との間
に挿入された出力抵抗器とを備えたトリガパルス
発生装置。 (2) 抵抗回路は、トランジスタのベース、エミ
ツタ間に逆極性に挿入されたダイオードであるこ
とを特徴とする実用新案登録請求の範囲第１項記
載のトリガパルス発生装置。[Claims for Utility Model Registration] (1) A pair of input terminals, a pair of grounded-emitter transistors whose bases are connected to these input terminals, and whose emitters are connected to each other and whose collectors are connected to each other, and these transistors. a pair of resistor circuits inserted between each of the bases and emitters, a pair of output terminals respectively connected to the connection point between the collectors and the connection point between the emitters, and a connection point between the DC power supply and the collectors; and an output resistor inserted between the trigger pulse generator and the trigger pulse generator. (2) The trigger pulse generator according to claim 1, wherein the resistor circuit is a diode inserted between the base and emitter of a transistor with opposite polarity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17267586U JPS63144730U (en) | 1986-11-12 | 1986-11-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17267586U JPS63144730U (en) | 1986-11-12 | 1986-11-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63144730U true JPS63144730U (en) | 1988-09-22 |
Family
ID=31109430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17267586U Pending JPS63144730U (en) | 1986-11-12 | 1986-11-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63144730U (en) |
-
1986
- 1986-11-12 JP JP17267586U patent/JPS63144730U/ja active Pending