JPS6383819U - - Google Patents
Info
- Publication number
- JPS6383819U JPS6383819U JP17886986U JP17886986U JPS6383819U JP S6383819 U JPS6383819 U JP S6383819U JP 17886986 U JP17886986 U JP 17886986U JP 17886986 U JP17886986 U JP 17886986U JP S6383819 U JPS6383819 U JP S6383819U
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- resistor
- resistors
- transistor
- ratio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Filters And Equalizers (AREA)
Description
第１図は本考案の実施例を示す回路図、第２図
は従来の時定数回路を示す回路図である。
Ｑ３０……第１のトランジスタ、Ｑ３１……第
２のトランジスタ、Ｑ３２……第３のトランジス
タ、Ｑ３３……第４のトランジスタ、Ｒ１……第
１の抵抗、Ｒ２……第２の抵抗、Ｒ３……第３の
抵抗、Ｒ４……第３の抵抗、１……帰還信号入力
端、Ｃ……コンデンサ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional time constant circuit. Q 30 ... first transistor, Q 31 ... second transistor, Q 32 ... third transistor, Q 33 ... fourth transistor, R 1 ... first resistor, R 2 ... third transistor 2 resistance, R 3 ... third resistance, R 4 ... third resistance, 1 ... feedback signal input terminal, C ... capacitor.
Claims (1)
し第４の抵抗を有し、第１のトランジスタとこれ
とは逆極性の第２のトランジスタとの夫々のコレ
クタを夫々第１及び第２の電源に接続し、第１及
び第２のトランジスタの各エミツタと帰還信号入
力端との間に相互に異なつた抵抗値の第１及び第
２の抵抗を夫々介挿し、前記第１及び第２のトラ
ンジスタのベースに夫々第３及び第４のトランジ
スタのベースを接続し、この第３及び第４のトラ
ンジスタのエミツタと信号出力端との間に相互に
異なつた抵抗値の第３及び第４の抵抗を夫々介挿
し、さらに前記信号出力端とアースとの間にコン
デンサを介挿し、前記第３の抵抗と第４の抵抗と
の比は前記第１の抵抗と第２の抵抗との比と同一
値であることを特徴とする時定数回路。 It has first to fourth transistors and first to fourth resistors, and the respective collectors of the first transistor and the second transistor having the opposite polarity are connected to the first and second power supplies, respectively. first and second resistors having mutually different resistance values are inserted between the respective emitters of the first and second transistors and the feedback signal input terminal, and the first and second transistors are connected to each other. The bases of third and fourth transistors are connected to the base, and third and fourth resistors having different resistance values are connected between the emitters of the third and fourth transistors and the signal output terminal, respectively. A capacitor is further inserted between the signal output terminal and the ground, and the ratio of the third resistor to the fourth resistor is the same as the ratio of the first resistor to the second resistor. A time constant circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17886986U JPS6383819U (en) | 1986-11-20 | 1986-11-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17886986U JPS6383819U (en) | 1986-11-20 | 1986-11-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6383819U true JPS6383819U (en) | 1988-06-01 |
Family
ID=31121406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17886986U Pending JPS6383819U (en) | 1986-11-20 | 1986-11-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6383819U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02195709A (en) * | 1989-01-24 | 1990-08-02 | Nec Ic Microcomput Syst Ltd | Time constant circuit |
-
1986
- 1986-11-20 JP JP17886986U patent/JPS6383819U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02195709A (en) * | 1989-01-24 | 1990-08-02 | Nec Ic Microcomput Syst Ltd | Time constant circuit |