JPS6249353U - - Google Patents
Info
- Publication number
- JPS6249353U JPS6249353U JP14068485U JP14068485U JPS6249353U JP S6249353 U JPS6249353 U JP S6249353U JP 14068485 U JP14068485 U JP 14068485U JP 14068485 U JP14068485 U JP 14068485U JP S6249353 U JPS6249353 U JP S6249353U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- transistor
- load resistor
- input stage
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Electronic Switches (AREA)
- Dc Digital Transmission (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Description
第１図はこの考案に係る回路装置の一実施例を
示す回路図、第２図は第１図の主要部のタイムチ
ヤート、第３図は従来の回路装置を示す回路図で
ある。
１…第１の回路、３…負荷抵抗、４…第２の回
路、５…トランジスタ、６，９…コンデンサ。
FIG. 1 is a circuit diagram showing an embodiment of the circuit device according to this invention, FIG. 2 is a time chart of the main part of FIG. 1, and FIG. 3 is a circuit diagram showing a conventional circuit device. DESCRIPTION OF SYMBOLS 1...First circuit, 3...Load resistance, 4...Second circuit, 5...Transistor, 6, 9...Capacitor.
Claims (1)
入力段にトランジスタ５を有し、前記第１の回路
１の出力側に直列接続される第２の回路４とを備
え、前記第１及び第２の回路１及び４の電源系統
を互に異ならしめてなる回路装置において、前記
第１の回路１の負荷抵抗３の両端子の夫々を、前
記第２の回路４の入力段のトランジスタ５のベー
ス及びエミツタの夫々にコンデンサ６，９を介し
て接続したことを特徴とする回路装置。 a first circuit 1 having a load resistor 3 in its output stage;
A transistor 5 is provided at the input stage, and a second circuit 4 is connected in series to the output side of the first circuit 1, and the power supply systems of the first and second circuits 1 and 4 are different from each other. In the circuit device, each of both terminals of the load resistor 3 of the first circuit 1 is connected to the base and emitter of a transistor 5 in the input stage of the second circuit 4 via capacitors 6 and 9, respectively. A circuit device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14068485U JPS6249353U (en) | 1985-09-17 | 1985-09-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14068485U JPS6249353U (en) | 1985-09-17 | 1985-09-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6249353U true JPS6249353U (en) | 1987-03-26 |
Family
ID=31047764
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14068485U Pending JPS6249353U (en) | 1985-09-17 | 1985-09-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6249353U (en) |
-
1985
- 1985-09-17 JP JP14068485U patent/JPS6249353U/ja active Pending
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