JPS61121017U - - Google Patents
Info
- Publication number
- JPS61121017U JPS61121017U JP389785U JP389785U JPS61121017U JP S61121017 U JPS61121017 U JP S61121017U JP 389785 U JP389785 U JP 389785U JP 389785 U JP389785 U JP 389785U JP S61121017 U JPS61121017 U JP S61121017U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- base
- current
- collector
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Amplifiers (AREA)
Description
第１図は、本考案の一実施例を示す回路図、第
２図は従来の電流ミラー回路を示す回路図、及び
第３図は本考案の別の実施例を示す回路図である
。
主な図番の説明、９……入力側トランジスタ、
１０……入力電流源、１１……出力側トランジス
タ、１３……第１制御トランジスタ、１４……第
２制御トランジスタ、１５……第３制御トランジ
スタ、１６……起動抵抗。
FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional current mirror circuit, and FIG. 3 is a circuit diagram showing another embodiment of the present invention. Explanation of main drawing numbers, 9... Input side transistor,
10... Input current source, 11... Output side transistor, 13... First control transistor, 14... Second control transistor, 15... Third control transistor, 16... Starting resistor.
Claims (1)
ンジスタと、該入力側トランジスタのベース電流
を定める第１制御トランジスタと、コレクタに負
荷が接続された出力側トランジスタと、ベース及
びエミツタが前記第１制御トランジスタと共通接
続され、前記ベース電流を定める第２制御トラン
ジスタと、ベースが前記入力側トランジスタのベ
ースに、コレクタが前記第１及び第２制御トラン
ジスタの共通ベースにそれぞれ接続されたＮＰＮ
型の第３制御トランジスタと、電源と前記第３制
御トランジスタのコレクタとの間に接続された起
動抵抗とから成り、前記出力側トランジスタのコ
レクタに前記入力電流源から供給される電流に応
じた電流を発生する様にしたことを特徴とする電
流ミラー回路。 an input transistor whose collector is connected to an input current source; a first control transistor that determines a base current of the input transistor; an output transistor whose collector is connected to a load; and whose base and emitter are connected to the first control transistor. a second control transistor that is commonly connected to and determines the base current; and an NPN whose base is connected to the base of the input transistor and whose collector is connected to the common base of the first and second control transistors, respectively.
and a starting resistor connected between a power source and the collector of the third control transistor, and a current corresponding to the current supplied from the input current source to the collector of the output transistor. A current mirror circuit characterized in that it generates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP389785U JPS61121017U (en) | 1985-01-16 | 1985-01-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP389785U JPS61121017U (en) | 1985-01-16 | 1985-01-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61121017U true JPS61121017U (en) | 1986-07-30 |
Family
ID=30478955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP389785U Pending JPS61121017U (en) | 1985-01-16 | 1985-01-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61121017U (en) |
-
1985
- 1985-01-16 JP JP389785U patent/JPS61121017U/ja active Pending