JPS61121019U - - Google Patents
Info
- Publication number
- JPS61121019U JPS61121019U JP577685U JP577685U JPS61121019U JP S61121019 U JPS61121019 U JP S61121019U JP 577685 U JP577685 U JP 577685U JP 577685 U JP577685 U JP 577685U JP S61121019 U JPS61121019 U JP S61121019U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- collector
- current
- base
- emitter path
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Amplifiers (AREA)
Description
第１図は、本考案の一実施例を示す回路図、第
２図は従来の電流ミラー回路を示す回路図、第３
図は本考案の別の実施例を示す回路図、及び第４
図は本考案の更に別の実施例を示す回路図である
。
主な図番の説明、９……第１トランジスタ、１
１……第２トランジスタ、１３……負帰還回路、
１８……制御トランジスタ、１９……ダイオード
。
Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a conventional current mirror circuit, and Fig. 3 is a circuit diagram showing an embodiment of the present invention.
The figure shows a circuit diagram showing another embodiment of the present invention, and a fourth
The figure is a circuit diagram showing yet another embodiment of the present invention. Explanation of main figure numbers, 9...First transistor, 1
1... Second transistor, 13 ... Negative feedback circuit,
18...control transistor, 19...diode.
Claims (1)
ンジスタを有する電流ミラー回路において、前記
第１トランジスタのコレクタ・ベース間に負帰還
回路を挿入するとともに、前記第２トランジスタ
のコレクタ・エミツタ路と直列に制御トランジス
タのコレクタ・エミツタ路を接続し、更に前記第
２トランジスタのベースと前記制御トランジスタ
のベースとの間にダイオードを接続して成り、前
記第１トランジスタのコレクタに接続された定電
流源に流れる電流に応じた電流を、前記第２トラ
ンジスタのコレクタから前記制御トランジスタの
コレクタ・エミツタ路を介して負荷に供給する様
にしたことを特徴とする電流ミラー回路。 In a current mirror circuit having first and second transistors connected in a current mirror relationship, a negative feedback circuit is inserted between the collector and base of the first transistor, and in series with the collector-emitter path of the second transistor. The collector-emitter path of the control transistor is connected, and a diode is connected between the base of the second transistor and the base of the control transistor, and the current flows into a constant current source connected to the collector of the first transistor. A current mirror circuit characterized in that a current corresponding to the current is supplied from the collector of the second transistor to the load via the collector-emitter path of the control transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP577685U JPS61121019U (en) | 1985-01-18 | 1985-01-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP577685U JPS61121019U (en) | 1985-01-18 | 1985-01-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61121019U true JPS61121019U (en) | 1986-07-30 |
Family
ID=30482596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP577685U Pending JPS61121019U (en) | 1985-01-18 | 1985-01-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61121019U (en) |
-
1985
- 1985-01-18 JP JP577685U patent/JPS61121019U/ja active Pending