JPS6320624U - - Google Patents
Info
- Publication number
- JPS6320624U JPS6320624U JP11230786U JP11230786U JPS6320624U JP S6320624 U JPS6320624 U JP S6320624U JP 11230786 U JP11230786 U JP 11230786U JP 11230786 U JP11230786 U JP 11230786U JP S6320624 U JPS6320624 U JP S6320624U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- potential terminal
- base
- terminal via
- collector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Power Conversion In General (AREA)
- Electronic Switches (AREA)
Description
第1図および第2図は本考案の第1および第2
の実施例を示す構成図、第3図は従来の一例を示
す構成図である。
1……高電位端、2……制御信号入力端、3…
…低電位端、4,7,12……抵抗、5,8,1
1,13……トランジスタ、6……基準電流源、
9……負荷、10……電圧源、20……カレント
ミラー回路。
Figures 1 and 2 are the first and second figures of the present invention.
Fig. 3 is a block diagram showing an example of the conventional system. 1...High potential end, 2...Control signal input end, 3...
...Low potential end, 4,7,12...Resistance, 5,8,1
1, 13...Transistor, 6...Reference current source,
9...Load, 10...Voltage source, 20...Current mirror circuit.
Claims (1)
かつ基準電流源を介して第2電位端子に接続され
るコレクタとベースとを短絡した第1トランジス
タと、エミツタを抵抗を介して前記第1電位端子
に接続しコレクタを負荷を介して前記第2電位端
子に接続しかつベースを前記第1トランジスタの
ベースに接続した第2トランジスタとから構成さ
れたカレントミラー回路と; エミツタを前記第2電位端子に接続しかつベー
スを制御信号入力電極とした第3トランジスタと
; エミツタを前記第3トランジスタのコレクタに
抵抗を介して接続しコレクタを前記第2トランジ
スタのエミツタに接続しかつベースを電圧源を介
して前記第2電位端子に接続した第4トランジス
タと; を備えることを特徴とするスイツチ回路。[Claims for Utility Model Registration] A first transistor whose emitter is connected to a first potential terminal via a resistor and whose collector and base are short-circuited and which is connected to a second potential terminal via a reference current source; a second transistor connected to the first potential terminal via a resistor, a collector connected to the second potential terminal via a load, and a base connected to the base of the first transistor; a third transistor whose emitter is connected to the second potential terminal and whose base is a control signal input electrode; the emitter is connected to the collector of the third transistor via a resistor, and the collector is connected to the emitter of the second transistor. and a fourth transistor whose base is connected to the second potential terminal via a voltage source.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11230786U JPH0513064Y2 (en) | 1986-07-21 | 1986-07-21 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11230786U JPH0513064Y2 (en) | 1986-07-21 | 1986-07-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6320624U true JPS6320624U (en) | 1988-02-10 |
JPH0513064Y2 JPH0513064Y2 (en) | 1993-04-06 |
Family
ID=30993056
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11230786U Expired - Lifetime JPH0513064Y2 (en) | 1986-07-21 | 1986-07-21 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0513064Y2 (en) |
-
1986
- 1986-07-21 JP JP11230786U patent/JPH0513064Y2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0513064Y2 (en) | 1993-04-06 |