JPS6316719U - - Google Patents
Info
- Publication number
- JPS6316719U JPS6316719U JP10935386U JP10935386U JPS6316719U JP S6316719 U JPS6316719 U JP S6316719U JP 10935386 U JP10935386 U JP 10935386U JP 10935386 U JP10935386 U JP 10935386U JP S6316719 U JPS6316719 U JP S6316719U
- Authority
- JP
- Japan
- Prior art keywords
- current
- transistors
- whose
- temperature dependent
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001419 dependent effect Effects 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 4
Description
第1図は本考案に係るヒステリシス回路の一実
施例を示す回路構成図、第2図〜第5図は本考案
の他の実施例を示す回路構成図、第6図は従来回
路の構成図、第7図はトランジスタのスイツチン
グ特性図である。
Q1〜Q7,Q30,Q31,Q60,Q61
,Q62,Q70,Q71……トランジスタ、R
……抵抗。
FIG. 1 is a circuit configuration diagram showing one embodiment of a hysteresis circuit according to the present invention, FIGS. 2 to 5 are circuit configuration diagrams showing other embodiments of the present invention, and FIG. 6 is a configuration diagram of a conventional circuit. , FIG. 7 is a switching characteristic diagram of the transistor. Q 1 to Q 7 , Q 30 , Q 31 , Q 60 , Q 61
, Q 62 , Q 70 , Q 71 ...transistor, R
……resistance.
Claims (1)
対トランジスタと、前記第2のトランジジスタの
ベースと直流電圧間に接続される抵抗と、前記第
2のトランジスタのコレクタに入力端が接続され
、ベースに出力端が接続されるカレントミラー回
路により構成される第1の電流源と、前記共通接
続された第1、第2のトランジスタのエミツタ並
びに前記第2のトランジスタのベースがそれぞれ
出力端に接続され、入力端には基準電流が供給さ
れるカレントミラー回路により構成される第2の
電流源とを具備するヒステリシス回路において、 前記第1もしくは第2の電流源の少なくともい
ずれか一方の電流源が供給する電流に温度依存性
を持たせることにより前記抵抗における電圧降下
を温度に依存させ、前記第1、第2のトランジス
タの温度依存特性に起因するヒステリシス出力電
圧の温度変動を相殺することを特徴とするヒステ
リシス回路。[Claims for Utility Model Registration] First and second differential pair transistors whose emitters are commonly connected; a resistor connected between the base of the second transistor and a DC voltage; a first current source constituted by a current mirror circuit whose input end is connected to the collector of the transistor and whose output end is connected to the base; emitters of the first and second transistors connected in common; and the second current source. A hysteresis circuit comprising a second current source constituted by a current mirror circuit whose bases of transistors are respectively connected to output terminals and whose input terminal is supplied with a reference current, wherein the first or second current The voltage drop across the resistor is made temperature dependent by making the current supplied by at least one of the current sources temperature dependent, and the hysteresis output is caused by the temperature dependent characteristics of the first and second transistors. A hysteresis circuit characterized by canceling temperature fluctuations in voltage.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10935386U JPS6316719U (en) | 1986-07-18 | 1986-07-18 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10935386U JPS6316719U (en) | 1986-07-18 | 1986-07-18 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6316719U true JPS6316719U (en) | 1988-02-03 |
Family
ID=30987373
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10935386U Pending JPS6316719U (en) | 1986-07-18 | 1986-07-18 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6316719U (en) |
-
1986
- 1986-07-18 JP JP10935386U patent/JPS6316719U/ja active Pending
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