JPS6378415U - - Google Patents
Info
- Publication number
- JPS6378415U JPS6378415U JP17108986U JP17108986U JPS6378415U JP S6378415 U JPS6378415 U JP S6378415U JP 17108986 U JP17108986 U JP 17108986U JP 17108986 U JP17108986 U JP 17108986U JP S6378415 U JPS6378415 U JP S6378415U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- collector
- base
- transistors
- anode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Amplifiers (AREA)
Description
第１図は本考案に係る反転型差動増幅回路の一
実施例を説明する為の回路図であり、第２図はそ
の一実施例を示す回路図である。第３図は一般的
な反転型差動増幅回路の例を示す回路図である。
１：差動増幅回路、２：基準電圧源、３：バイ
アス電圧源、４：入力端子、５：定電流源回路、
６：出力端子、７，８：電流ミラー回路からなる
能動負荷回路。
FIG. 1 is a circuit diagram for explaining one embodiment of an inverting differential amplifier circuit according to the present invention, and FIG. 2 is a circuit diagram showing one embodiment thereof. FIG. 3 is a circuit diagram showing an example of a general inverting differential amplifier circuit. 1: Differential amplifier circuit, 2: Reference voltage source, 3: Bias voltage source, 4: Input terminal, 5: Constant current source circuit,
6: Output terminal, 7, 8: Active load circuit consisting of a current mirror circuit.
Claims (1)
子に入力信号が供給される差動対をなす第１と第
２のトランジスタと定電流源回路からなる差動増
幅回路と、該差動増幅回路から互いに位相の反転
した出力を導出する出力段に第３と第４のトラン
ジスタを具えた第１の能動負荷回路と出力段に第
５と第６のトランジスタを具えた第２の能動負荷
回路とを具えており、該第３のトランジスタのコ
レクタが第１のダイオードのアノードに接続され
、その接続点が第７のトランジスタのベースに接
続され、該第７のトランジスタのコレクタが該第
５のトランジスタのコレクタに接続されると共に
出力端子４に接続され、該第４のトランジスタの
コレクタが第８のトランジスタのコレクタに接続
され、そのベースが第４のダイオードのアノード
に接続されると共に該第６のトランジスタのコレ
クタに接続され、該第１のトランジスタのベース
に第１と第２の抵抗が接続され、該第１の抵抗の
他端が入力端子に接続されると共に該第４と第８
のトランジスタのコレクタに接続され、該第２の
抵抗の他端が該第５と第７のトランジスタのコレ
クタに接続されると共に出力端子に接続されたこ
とを特徴とする反転型差動増幅回路。 A differential amplifier circuit comprising first and second transistors forming a differential pair and a constant current source circuit, in which a reference voltage source is supplied to one input terminal and an input signal is supplied to the other input terminal; A first active load circuit including third and fourth transistors in the output stage and a second active load circuit including fifth and sixth transistors in the output stage for deriving outputs with mutually inverted phases from the circuit. The collector of the third transistor is connected to the anode of the first diode, the connection point thereof is connected to the base of the seventh transistor, and the collector of the seventh transistor is connected to the anode of the first diode. The collector of the fourth transistor is connected to the collector of the eighth transistor, and the base of the fourth transistor is connected to the anode of the fourth diode. is connected to the collector of the transistor, first and second resistors are connected to the base of the first transistor, the other end of the first resistor is connected to the input terminal, and the fourth and eighth resistors are connected to the base of the first transistor.
an inverting differential amplifier circuit, characterized in that the second resistor is connected to the collector of the fifth transistor, and the other end of the second resistor is connected to the collectors of the fifth and seventh transistors, and also connected to the output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17108986U JPH0438568Y2 (en) | 1986-11-07 | 1986-11-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17108986U JPH0438568Y2 (en) | 1986-11-07 | 1986-11-07 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6378415U true JPS6378415U (en) | 1988-05-24 |
| JPH0438568Y2 JPH0438568Y2 (en) | 1992-09-09 |
Family
ID=31106405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17108986U Expired JPH0438568Y2 (en) | 1986-11-07 | 1986-11-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0438568Y2 (en) |
-
1986
- 1986-11-07 JP JP17108986U patent/JPH0438568Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0438568Y2 (en) | 1992-09-09 |