JPS63147030U - - Google Patents
Info
- Publication number
- JPS63147030U JPS63147030U JP4010487U JP4010487U JPS63147030U JP S63147030 U JPS63147030 U JP S63147030U JP 4010487 U JP4010487 U JP 4010487U JP 4010487 U JP4010487 U JP 4010487U JP S63147030 U JPS63147030 U JP S63147030U
- Authority
- JP
- Japan
- Prior art keywords
- mos transistor
- transistor
- drain
- potential
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 4
Description
第１図は本考案の一実施例の回路図、第２図及
び第３図は第１図のシユミツト回路の特性図、第
４図は従来例の回路図、第５図は第２図のシユミ
ツト回路の動作を示すタイミングチヤートである
。
１，３，５…ＮＭＯＳトランジスタ、２，４，
６…ＰＭＯＳトランジスタ、１１，１２…２入力
ＮＡＮＤ回路、１３，１４，１５…インバータ。
Fig. 1 is a circuit diagram of one embodiment of the present invention, Figs. 2 and 3 are characteristic diagrams of the Schmitts circuit of Fig. 1, Fig. 4 is a circuit diagram of a conventional example, and Fig. 5 is a circuit diagram of the Schmitt circuit of Fig. 2. This is a timing chart showing the operation of the Schmitt circuit. 1, 3, 5...NMOS transistor, 2, 4,
6... PMOS transistor, 11, 12... 2-input NAND circuit, 13, 14, 15... inverter.
Claims (1)
ネルの第１のＭＯＳトランジスタのソースとを接
続し、前記第１のＭＯＳトランジスタのドレイン
と出力端子とを接続し、第２の電位とＰ型、Ｎ型
の他方の導電型チヤンネルの第２のＭＯＳトラン
ジスタのソースとを接続し、前記第２のＭＯＳト
ランジスタのドレインと前記出力端子とを接続し
、前記第１の電位と前記一方の導電型チヤンネル
の第３のＭＯＳトランジスタのソースとを接続し
、前記第１のＭＯＳトランジスタのゲートと前記
第３のＭＯＳトランジスタのドレインとを接続し
、前記第２の電位と前記他方の導電型チヤンネル
の第４のＭＯＳトランジスタのソースとを接続し
、前記第２のＭＯＳトランジスタのゲートと前記
第４のＭＯＳトランジスタのドレインとを接続し
、前記第３及び第４のＭＯＳトランジスタのゲー
トと前記出力端子とを各々接続し、前記第１の電
位と前記一方の導電型チヤンネルの第５のＭＯＳ
トランジスタのソースとを接続し、前記第２のＭ
ＯＳトランジスタのゲートと前記第５のＭＯＳト
ランジスタのドレインとを接続し、前記第２の電
位と前記他方の導電型チヤンネルの第６のＭＯＳ
トランシズタのソースとを接続し、前記第１のＭ
ＯＳトランジスタのゲートと前記第６のＭＯＳト
ランジスタのドレインとを接続し、前記第５及び
第６のＭＯＳトランジスタのゲートに入力信号を
供給するようにしてなることを特徴とするシユミ
ツト回路。 A first potential is connected to the source of the first MOS transistor of one of the P-type and N-type conductivity channels, the drain of the first MOS transistor is connected to the output terminal, and the second potential and The source of the second MOS transistor of the other conductivity type channel of P type and N type is connected, the drain of the second MOS transistor is connected to the output terminal, and the first potential and the one of the channels are connected. the source of the third MOS transistor of the conductivity type channel is connected, the gate of the first MOS transistor is connected to the drain of the third MOS transistor, and the second potential is connected to the source of the third MOS transistor of the other conductivity type channel. , the gate of the second MOS transistor and the drain of the fourth MOS transistor are connected, and the gates of the third and fourth MOS transistors are connected to the output terminal. a fifth MOS of the first conductivity type channel and the first potential of the one conductivity type channel;
the source of the transistor, and the second M
The gate of the OS transistor and the drain of the fifth MOS transistor are connected, and the second potential and the sixth MOS transistor of the other conductivity type channel are connected.
the source of the transistor, and the first M
A Schmitt circuit characterized in that the gate of the OS transistor and the drain of the sixth MOS transistor are connected, and an input signal is supplied to the gates of the fifth and sixth MOS transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4010487U JPH066623Y2 (en) | 1987-03-18 | 1987-03-18 | Schmitt circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4010487U JPH066623Y2 (en) | 1987-03-18 | 1987-03-18 | Schmitt circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63147030U true JPS63147030U (en) | 1988-09-28 |
| JPH066623Y2 JPH066623Y2 (en) | 1994-02-16 |
Family
ID=30853889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4010487U Expired - Lifetime JPH066623Y2 (en) | 1987-03-18 | 1987-03-18 | Schmitt circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH066623Y2 (en) |
-
1987
- 1987-03-18 JP JP4010487U patent/JPH066623Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH066623Y2 (en) | 1994-02-16 |
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