JPS58194541U - signal input circuit - Google Patents
signal input circuitInfo
- Publication number
- JPS58194541U JPS58194541U JP9151082U JP9151082U JPS58194541U JP S58194541 U JPS58194541 U JP S58194541U JP 9151082 U JP9151082 U JP 9151082U JP 9151082 U JP9151082 U JP 9151082U JP S58194541 U JPS58194541 U JP S58194541U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- signal input
- whose
- transistor
- input circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のプルアップ抵抗回路、第２図は従来のプ
ルアップ抵抗回路１、第３図は本考案による信号入力回
路である。
３３−１・・・Ｐ型ＭＯ３）ランジスタ、３３−２・・
・Ｎ型ＭＯＳトランジスタ、３４・・・インバータ回路
。FIG. 1 shows a conventional pull-up resistor circuit, FIG. 2 shows a conventional pull-up resistor circuit 1, and FIG. 3 shows a signal input circuit according to the present invention. 33-1...P-type MO3) transistor, 33-2...
・N-type MOS transistor, 34...inverter circuit.
Claims (1)
接続しゲート電極を第１の制御信号に接続するＰチャン
ネルＭＯ３ＦＥＴ）ランジスタと、ソース側をＧＮＤに
ドレイン側を入力信号ラインに接続しゲート電極を第２
の制御信号に接続するＮチャンネル型ＭＯ３ＦＥＴ）ラ
ンジスタと、信号入力ラインの信号を反転して出力する
インバータとを有し、前記各制御信号により少なくとも
一方のトランジスタを非導通とすることを特徴とする信
号入力回路。' A P-channel MO3FET transistor whose source side is connected to the power supply, whose drain side is connected to the input signal line, and whose gate electrode is connected to the first control signal, and whose source side is connected to GND, whose drain side is connected to the input signal line, and whose gate electrode is Second
The transistor is characterized in that it has an N-channel MO3FET) transistor connected to the control signal of the signal input line, and an inverter that inverts and outputs the signal of the signal input line, and at least one of the transistors is rendered non-conductive by each of the control signals. Signal input circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9151082U JPS58194541U (en) | 1982-06-21 | 1982-06-21 | signal input circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9151082U JPS58194541U (en) | 1982-06-21 | 1982-06-21 | signal input circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58194541U true JPS58194541U (en) | 1983-12-24 |
Family
ID=30099872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9151082U Pending JPS58194541U (en) | 1982-06-21 | 1982-06-21 | signal input circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58194541U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0191521A (en) * | 1987-10-02 | 1989-04-11 | Kawasaki Steel Corp | Programmable input circuit |
-
1982
- 1982-06-21 JP JP9151082U patent/JPS58194541U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0191521A (en) * | 1987-10-02 | 1989-04-11 | Kawasaki Steel Corp | Programmable input circuit |
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