JPS5956823U - CMOS circuit - Google Patents
CMOS circuitInfo
- Publication number
- JPS5956823U JPS5956823U JP15034582U JP15034582U JPS5956823U JP S5956823 U JPS5956823 U JP S5956823U JP 15034582 U JP15034582 U JP 15034582U JP 15034582 U JP15034582 U JP 15034582U JP S5956823 U JPS5956823 U JP S5956823U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- protection diode
- input protection
- cmos circuit
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はこの考案の実施例のＣＭＯ３回路の回路図であ
る。第２図は上記ＣＭＯ３回路の一部の概略構造図であ
る。第３図はバイアス回路−例の回路図である。第４図
は上記バイアス回路の等価回路図である。
１・・・ＰチャネルＭＯ３−ＦＥＴ、２・・・Ｎチャネ
ルＭＯ５，ＦＥＴ、 ３． ４・・・入力保護ダイオー
ド、５゜６・・・バイアス回路、７・・・発振回路。FIG. 1 is a circuit diagram of a CMO3 circuit according to an embodiment of this invention. FIG. 2 is a schematic structural diagram of a part of the CMO3 circuit. FIG. 3 is a circuit diagram of an example bias circuit. FIG. 4 is an equivalent circuit diagram of the bias circuit. 1...P channel MO3-FET, 2...N channel MO5, FET, 3. 4... Input protection diode, 5゜6... Bias circuit, 7... Oscillation circuit.
Claims (1)
も一方のゲートと電源間に入力保護ダイオードを接続し
たＣＭＯ５回路において、前記入力保ダイオードと前記
電源間に前記入力保護ダイオードに逆バイアス電圧を与
えるバイアス回路を接続したことを特徴とするＣＭＯ３
回路。In a CMO5 circuit in which an input protection diode is connected between the gate of at least one of the P-channel or N-channel MO3, FET and the power supply, a bias circuit that applies a reverse bias voltage to the input protection diode is connected between the input protection diode and the power supply. CMO3 characterized by
circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15034582U JPS5956823U (en) | 1982-09-30 | 1982-09-30 | CMOS circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15034582U JPS5956823U (en) | 1982-09-30 | 1982-09-30 | CMOS circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5956823U true JPS5956823U (en) | 1984-04-13 |
Family
ID=30333482
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15034582U Pending JPS5956823U (en) | 1982-09-30 | 1982-09-30 | CMOS circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5956823U (en) |
-
1982
- 1982-09-30 JP JP15034582U patent/JPS5956823U/en active Pending
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