JPS62109512U - - Google Patents
Info
- Publication number
- JPS62109512U JPS62109512U JP20048185U JP20048185U JPS62109512U JP S62109512 U JPS62109512 U JP S62109512U JP 20048185 U JP20048185 U JP 20048185U JP 20048185 U JP20048185 U JP 20048185U JP S62109512 U JPS62109512 U JP S62109512U
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- bias power
- drain
- mosfet
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000009977 dual effect Effects 0.000 claims description 3
- 230000000295 complement effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 8
Landscapes
- Amplifiers (AREA)
Description
第１図はこの考案の半導体増幅器の一実施例を
示す回路図、第２図はＮチヤネルエンハンスメン
ト形の第１のデユアルゲートＭＯＳＦＥＴの動作
を説明するための特性図、第３図はＰチヤネルエ
ンハンスメント形の第２のデユアルゲートＭＯＳ
ＦＥＴの動作を説明するための特性図、第４図お
よび第５図はこの考案の半導体増幅器の作用を説
明するための出力信号波形図、第６図は従来の半
導体増幅器を示す回路図、第７図はＮチヤネルエ
ンハンスメント形の第１のＭＯＳＦＥＴの動作を
説明するための特性図、第８図はＰチヤネルエン
ハンスメント形の第２のＭＯＳＦＥＴの動作を説
明するための特性図、第９図、第１０図、第１１
図、第１２図および第１３図は従来の半導体増幅
器の動作を説明するための図である。
図において、３は第１のドレインバイアス電源
、４は負荷、５は第２のドレインバイアス電源、
１０は第１のデユアルゲートＭＯＳＦＥＴ、１１
は第２のデユアルゲートＭＯＳＦＥＴ、１２は第
１の可変ゲートバイアス電源、１３は第２の可変
ゲートバイアス電源である。なお、各図中の同一
符号は同一または相当部分を示す。
Fig. 1 is a circuit diagram showing one embodiment of the semiconductor amplifier of this invention, Fig. 2 is a characteristic diagram for explaining the operation of the first dual-gate MOSFET of N-channel enhancement type, and Fig. 3 is a P-channel enhancement type MOSFET. The second dual gate MOS of the shape
FIGS. 4 and 5 are characteristic diagrams for explaining the operation of the FET, output signal waveform diagrams for explaining the operation of the semiconductor amplifier of this invention, FIG. 6 is a circuit diagram showing a conventional semiconductor amplifier, and FIG. 7 is a characteristic diagram for explaining the operation of the first MOSFET of N-channel enhancement type, FIG. 8 is a characteristic diagram for explaining the operation of the second MOSFET of P-channel enhancement type, and FIGS. Figures 10 and 11
12 and 13 are diagrams for explaining the operation of a conventional semiconductor amplifier. In the figure, 3 is the first drain bias power supply, 4 is the load, 5 is the second drain bias power supply,
10 is the first dual gate MOSFET, 11
is a second dual-gate MOSFET, 12 is a first variable gate bias power supply, and 13 is a second variable gate bias power supply. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
れ、ソースが互いに接続されて接地された相補の
対をなす第１および第２のＭＯＳＦＥＴと、その
一端が前記第１および第２のＭＯＳＦＥＴのソー
ス間に接続された負荷と、この負荷の他端と前記
第１のＭＯＳＦＥＴのドレイン間に接続された第
１のドレインバイアス電源と、前記負荷の他端と
前記第２のＭＯＳＦＥＴのドレイン間に接続され
た第２のドレインバイアス電源とから構成される
半導体増幅器において、前記第１および第２のＭ
ＯＳＦＥＴの少なくとも一方をデユアルゲートＭ
ＯＳＦＥＴとし、そのゲートの一端を可変ゲート
バイアス電源に接続したことを特徴とする半導体
増幅器。 first and second MOSFETs forming a complementary pair whose gates are connected to each other and connected to a signal source, and whose sources are connected to each other and grounded; and one end thereof is connected between the sources of the first and second MOSFETs. a first drain bias power supply connected between the other end of the load and the drain of the first MOSFET; and a first drain bias power supply connected between the other end of the load and the drain of the second MOSFET. and a second drain bias power supply, wherein the first and second M
Dual gate M for at least one of the OSFETs
A semiconductor amplifier characterized in that it is an OSFET, and one end of its gate is connected to a variable gate bias power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20048185U JPS62109512U (en) | 1985-12-26 | 1985-12-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20048185U JPS62109512U (en) | 1985-12-26 | 1985-12-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62109512U true JPS62109512U (en) | 1987-07-13 |
Family
ID=31163028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20048185U Pending JPS62109512U (en) | 1985-12-26 | 1985-12-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62109512U (en) |
-
1985
- 1985-12-26 JP JP20048185U patent/JPS62109512U/ja active Pending
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