JPH0178433U - - Google Patents
Info
- Publication number
- JPH0178433U JPH0178433U JP1987174695U JP17469587U JPH0178433U JP H0178433 U JPH0178433 U JP H0178433U JP 1987174695 U JP1987174695 U JP 1987174695U JP 17469587 U JP17469587 U JP 17469587U JP H0178433 U JPH0178433 U JP H0178433U
- Authority
- JP
- Japan
- Prior art keywords
- mosfet
- channel
- gate
- connection point
- channel type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Description
第１図は本考案の実施例を示す回路図、第２図
は従来例を示す回路図である。
６……第１ＭＯＳＦＥＴ、７……第２ＭＯＳＦ
ＥＴ、８……第３ＭＯＳＦＥＴ、９……第４ＭＯ
ＳＦＥＴ、１０……出力用ＰチヤンネルＭＯＳＦ
ＥＴ、１１……出力用ＮチヤンネルＭＯＳＦＥＴ
、１２……Ｃ―ＭＯＳインバータ、１５……遅延
回路。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional example. 6...1st MOSFET, 7...2nd MOSFET
ET, 8...3rd MOSFET, 9...4th MO
SFET, 10...P channel MOSF for output
ET, 11...N-channel MOSFET for output
, 12...C-MOS inverter, 15...delay circuit.
Claims (1)
信号がゲートに共通に印加されたＰチヤンネル型
の第１ＭＯＳＦＥＴ、Ｎチヤンネル型の第２のＭ
ＯＳＦＥＴ、Ｐチヤンネル型第３ＭＯＳＦＥＴ、
Ｎチヤンネル型の第４ＭＯＳＦＥＴと、前記入力
信号を遅延する遅延回路と、該遅延回路の出力を
入力し出力が前記第２ＭＯＳＦＥＴと第３ＭＯＳ
ＦＥＴの接続点に接続されたＣ―ＭＯＳインバー
タと、前記第１ＭＯＳＦＥＴと第２ＭＯＳＦＥＴ
の接続点にＰチヤンネル側のゲートが接続され、
前記第３ＭＯＳＦＥＴと第４ＭＯＳＦＥＴの接続
点にＮチヤンネル側のゲートが接続されたＣ―Ｍ
ＯＳ回路とを備えて成るＣ―ＭＯＳドライバー回
路。 A first MOSFET of P channel type connected in series between a first potential and a second potential and having an input signal commonly applied to the gate, and a second MOSFET of N channel type.
OSFET, P channel type 3rd MOSFET,
a fourth N-channel MOSFET; a delay circuit that delays the input signal; an output of the delay circuit is input and the output is connected to the second MOSFET and the third MOSFET;
a C-MOS inverter connected to a connection point of the FET, and the first MOSFET and the second MOSFET.
The gate on the P channel side is connected to the connection point of
A C-M in which the gate on the N channel side is connected to the connection point between the third MOSFET and the fourth MOSFET.
A C-MOS driver circuit comprising an OS circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987174695U JPH0178433U (en) | 1987-11-16 | 1987-11-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987174695U JPH0178433U (en) | 1987-11-16 | 1987-11-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0178433U true JPH0178433U (en) | 1989-05-26 |
Family
ID=31466536
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987174695U Pending JPH0178433U (en) | 1987-11-16 | 1987-11-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0178433U (en) |
-
1987
- 1987-11-16 JP JP1987174695U patent/JPH0178433U/ja active Pending