JPS63147036U - - Google Patents
Info
- Publication number
- JPS63147036U JPS63147036U JP4021787U JP4021787U JPS63147036U JP S63147036 U JPS63147036 U JP S63147036U JP 4021787 U JP4021787 U JP 4021787U JP 4021787 U JP4021787 U JP 4021787U JP S63147036 U JPS63147036 U JP S63147036U
- Authority
- JP
- Japan
- Prior art keywords
- channel
- channel mos
- mos transistor
- inverter
- mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Logic Circuits (AREA)
Description
第１図は本考案の実施例を示す回路図、第２図
は従来例を示す回路図である。
７…出力ドライバ、８…第１のＣ―ＭＯＳイン
バータ、９…第２のＣ―ＭＯＳインバータ、１０
…遅延回路。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional example. 7... Output driver, 8... First C-MOS inverter, 9... Second C-MOS inverter, 10
...Delay circuit.
Claims (1)
ジスタから成る出力ドライバと、入力信号が印加
され出力が前記ＰチヤンネルＭＯＳトランジスタ
のゲートに印加された第１のＣ―ＭＯＳインバー
タと、入力信号が印加され出力が前記Ｎチヤンネ
ルＭＯＳトランジスタのゲートに印加された第２
のＣ―ＭＯＳインバータと、前記第１のＣ―ＭＯ
ＳインバータのＮチヤンネルＭＯＳトランジスタ
と直列接続されたＮチヤンネルＭＯＳトランジス
タと、前記第２のＣ―ＭＯＳインバータのＰチヤ
ンネルＭＯＳトランジスタと直列接続されたＰチ
ヤンネルＭＯＳトランジスタと、前記入力信号が
印加され出力が前記第１及び第２のＣ―ＭＯＳイ
ンバータと直列接続されたＮチヤンネル及びＰチ
ヤンネルのＭＯＳトランジスタのゲートに印加さ
れた遅延回路とを備えた出力バツフア回路。 an output driver consisting of P-channel and N-channel MOS transistors; a first C-MOS inverter to which an input signal is applied and whose output is applied to the gate of the P-channel MOS transistor; The second voltage applied to the gate of the channel MOS transistor
a C-MOS inverter, and the first C-MOS
An N-channel MOS transistor connected in series with the N-channel MOS transistor of the S-inverter, and a P-channel MOS transistor connected in series with the P-channel MOS transistor of the second C-MOS inverter, to which the input signal is applied and the output is An output buffer circuit comprising a delay circuit applied to the gates of N-channel and P-channel MOS transistors connected in series with the first and second C-MOS inverters.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4021787U JPS63147036U (en) | 1987-03-19 | 1987-03-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4021787U JPS63147036U (en) | 1987-03-19 | 1987-03-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63147036U true JPS63147036U (en) | 1988-09-28 |
Family
ID=30854108
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4021787U Pending JPS63147036U (en) | 1987-03-19 | 1987-03-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63147036U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61214817A (en) * | 1985-03-20 | 1986-09-24 | Toshiba Corp | Cmos integrated circuit |
-
1987
- 1987-03-19 JP JP4021787U patent/JPS63147036U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61214817A (en) * | 1985-03-20 | 1986-09-24 | Toshiba Corp | Cmos integrated circuit |
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