JPH0446724U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an integrated circuit device according to one embodiment of this invention, FIG. 2 is a circuit diagram showing an integrated circuit device according to another embodiment of this invention, and FIG. 3 is a circuit diagram showing an integrated circuit device according to another embodiment of this invention.
4 is a timing diagram showing signal changes in the circuit shown in FIG. 2, FIG. 5 is a circuit diagram of a conventional integrated circuit device, and FIG. 6 is a timing diagram showing signal changes in the circuit shown in FIG. , the gate-source voltage VGS in the P-channel transistor
A diagram showing the outline of the VGS-IDS characteristic curve of the drain-source voltage VDS and drain-source current IDS when fixed. Figure 7 shows the VGS-ID when VDS is fixed in N, P channel transistors.
FIG. 3 is a diagram showing the outline of an S characteristic curve and showing how a through current is generated. 1 is an input signal, 2 is an output signal, 3 is a power supply, 4 is a ground, 5 and 10 are CMOS P channels,
6 and 11 are N channels, 7 is buffer, 8 is N
9, 13 and 15 are NOR, 13 and 16 are inverters, and 14 is AND. In addition, in the figure,
The same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] It is characterized by being equipped with a logic circuit composed of CMOS and a combination circuit for converting the same signal into two temporally independent signals and applying the same signal to the gate inputs of the N-channel and P-channel transistors of the same element. integrated circuit device.