JPS63173925U - - Google Patents
Info
- Publication number
- JPS63173925U JPS63173925U JP6843787U JP6843787U JPS63173925U JP S63173925 U JPS63173925 U JP S63173925U JP 6843787 U JP6843787 U JP 6843787U JP 6843787 U JP6843787 U JP 6843787U JP S63173925 U JPS63173925 U JP S63173925U
- Authority
- JP
- Japan
- Prior art keywords
- gate
- signal line
- mos transistor
- bias circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 7
Landscapes
- Electronic Switches (AREA)
- Logic Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
第１図は、プルアツプ素子としてＰＭＯＳＦＥ
Ｔを用いたこの考案の１実施例である半導体集積
回路装置の回路図、第２図は、プルダウン素子と
してＮＭＯＳＦＥＴを用いたこの考案の他の実施
例である半導体集積回路装置の回路図、第３図は
、プルアツプ素子として、ＰＭＯＳＦＥＴを用い
、バイアス回路内にＮＭＯＳＦＥＴを用いたこの
考案のさらに他の実施例である半導体集積回路装
置の回路図、第４図は、ＭＯＳＦＥＴのスレツシ
ヨールド電圧を決定するためのデータを計測する
原理的な回路図、第５図は、Ｖ―Ｉ特性曲線とＭ
ＯＳＦＥＴのスレツシヨールド電圧との関係を示
した図、第６図は、従来のプルアツプ素子の原理
を示した図、第７図はプルアツプ素子として、Ｍ
ＯＳＦＥＴを使用した従来の半導体集積回路装置
の回路図である。
１……ＰＭＯＳＦＥＴ、１′……ＮＭＯＳＦＥ
Ｔ、２……バイアス回路、３……信号入力端子、
４……信号線、５……インバータ、６……出力端
子、７……電源ライン、８……ＮＭＯＳＦＥＴ、
９……電源ライン。
Figure 1 shows a PMOSFE as a pull-up element.
FIG. 2 is a circuit diagram of a semiconductor integrated circuit device which is an embodiment of this invention using T. Fig. 3 is a circuit diagram of a semiconductor integrated circuit device which is still another embodiment of this invention using a PMOSFET as a pull-up element and an NMOSFET in a bias circuit, and Fig. 4 shows a circuit diagram for determining the threshold voltage of the MOSFET. Figure 5 shows the principle circuit diagram for measuring data for V-I characteristic curve and M
Figure 6 is a diagram showing the relationship between the threshold voltage of OSFET, and Figure 7 is a diagram showing the principle of a conventional pull-up element.
1 is a circuit diagram of a conventional semiconductor integrated circuit device using an OSFET. 1...PMOSFET, 1'...NMOSFE
T, 2...bias circuit, 3...signal input terminal,
4... Signal line, 5... Inverter, 6... Output terminal, 7... Power line, 8... NMOSFET,
9...Power line.
Claims (1)
続し、ドレインを信号ラインに接続するとともに
、ゲートをバイアス回路に接続し、前記バイアス
回路によりゲートを上記ＭＯＳトランジスタのス
レツシヨールド電圧｜Ｖｔｈ｜付近にバイアスし
て、上記信号ラインをプルアツプまたはプルダウ
ンすることを特徴とする半導体集積回路装置。 The source of the MOS transistor is connected to a power supply line, the drain is connected to a signal line, and the gate is connected to a bias circuit, and the gate is biased near the threshold voltage |V th | of the MOS transistor by the bias circuit, A semiconductor integrated circuit device characterized in that the signal line is pulled up or pulled down.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6843787U JPS63173925U (en) | 1987-05-07 | 1987-05-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6843787U JPS63173925U (en) | 1987-05-07 | 1987-05-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63173925U true JPS63173925U (en) | 1988-11-11 |
Family
ID=30908255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6843787U Pending JPS63173925U (en) | 1987-05-07 | 1987-05-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63173925U (en) |
-
1987
- 1987-05-07 JP JP6843787U patent/JPS63173925U/ja active Pending
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