JPS63120419U - - Google Patents

Info

Publication number
JPS63120419U
JPS63120419U JP1001687U JP1001687U JPS63120419U JP S63120419 U JPS63120419 U JP S63120419U JP 1001687 U JP1001687 U JP 1001687U JP 1001687 U JP1001687 U JP 1001687U JP S63120419 U JPS63120419 U JP S63120419U
Authority
JP
Japan
Prior art keywords
voltage
semiconductor device
transistor
drain
input circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1001687U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1001687U priority Critical patent/JPS63120419U/ja
Publication of JPS63120419U publication Critical patent/JPS63120419U/ja
Pending legal-status Critical Current

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の半導体装置の入力回路の一実
施例の回路図、第2図は第1図示の回路の入出力
信号波形図、第3図は本考案回路の使用状態を説
明するための図、第4図は従来回路の一例の回路
図、第5図は従来回路の入出力信号波形図である
。 図中において、31はFET(電界効果トラン
ジスタ)、33は抵抗である。
Fig. 1 is a circuit diagram of one embodiment of the input circuit of the semiconductor device of the present invention, Fig. 2 is an input/output signal waveform diagram of the circuit shown in Fig. 1, and Fig. 3 is for explaining the usage state of the circuit of the present invention. FIG. 4 is a circuit diagram of an example of a conventional circuit, and FIG. 5 is an input/output signal waveform diagram of the conventional circuit. In the figure, 31 is an FET (field effect transistor), and 33 is a resistor.

Claims (1)

【実用新案登録請求の範囲】 ゲートに第1の電圧が印加された電界効果トラ
ンジスタのソースに該第1の電圧よりも高い第2
の電圧と、該第1の電圧よりも低い第3の電圧と
の間で振幅する入力信号をうけ、該入力信号がス
レツシヨールド電圧を越えたときにのみ導通し、
該トランジスタのドレインから前記第1の電圧と
それよりも高い電圧の間で振幅するデイジタル信
号を半導体装置に供給する半導体装置の入力回路
において、 該トランジスタのドレインに一端を接続され、
他端に前記第1の電圧が印加された抵抗を有して
なる半導体装置の入力回路。
[Claims for Utility Model Registration] A second voltage higher than the first voltage is applied to the source of a field effect transistor whose gate is applied with a first voltage.
and a third voltage lower than the first voltage, and conducts only when the input signal exceeds a threshold voltage;
In an input circuit of a semiconductor device that supplies a digital signal that swings between the first voltage and a higher voltage from the drain of the transistor to the semiconductor device, one end is connected to the drain of the transistor;
An input circuit for a semiconductor device comprising a resistor to which the first voltage is applied to the other end.
JP1001687U 1987-01-27 1987-01-27 Pending JPS63120419U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1001687U JPS63120419U (en) 1987-01-27 1987-01-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1001687U JPS63120419U (en) 1987-01-27 1987-01-27

Publications (1)

Publication Number Publication Date
JPS63120419U true JPS63120419U (en) 1988-08-04

Family

ID=30795919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1001687U Pending JPS63120419U (en) 1987-01-27 1987-01-27

Country Status (1)

Country Link
JP (1) JPS63120419U (en)

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