JPS629825U - - Google Patents

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Publication number
JPS629825U
JPS629825U JP10221985U JP10221985U JPS629825U JP S629825 U JPS629825 U JP S629825U JP 10221985 U JP10221985 U JP 10221985U JP 10221985 U JP10221985 U JP 10221985U JP S629825 U JPS629825 U JP S629825U
Authority
JP
Japan
Prior art keywords
gate circuit
input gate
external terminal
voltage
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10221985U
Other languages
Japanese (ja)
Other versions
JPH0449706Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985102219U priority Critical patent/JPH0449706Y2/ja
Publication of JPS629825U publication Critical patent/JPS629825U/ja
Application granted granted Critical
Publication of JPH0449706Y2 publication Critical patent/JPH0449706Y2/ja
Expired legal-status Critical Current

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  • Microcomputers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の実施例を示す回路図、第２図
は従来の使用例を示す回路図である。 ９…入力ゲート回路、１０，１１，１５…Ｐチ
ヤンネルＭＯＳＦＥＴ、１２，１３，１６…Ｎチ
ヤンネルＭＯＳＦＥＴ、１４，１８…インバータ
、１７…入力端子。 FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional usage example. 9... Input gate circuit, 10, 11, 15... P channel MOSFET, 12, 13, 16... N channel MOSFET, 14, 18... Inverter, 17... Input terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電源電圧よりも大きな電圧を印加可能な外部端
子と、該外部端子からの信号を受け取る入力ゲー
ト回路と、該入力ゲート回路と前記外部端子間に
設けられた高耐圧のＭＯＳＦＥＴと、前記入力ゲ
ート回路に設けられたプルダウンあるいはプルア
ツプＭＯＳＦＥＴとを備え、ホールドモード時に
前記入力ゲート回路の入力を禁止する制御信号を
前記高耐圧のＭＯＳＦＥＴのゲートに印加するこ
とを特徴とする半導体集積回路。 an external terminal capable of applying a voltage greater than a power supply voltage; an input gate circuit that receives a signal from the external terminal; a high-voltage MOSFET provided between the input gate circuit and the external terminal; and the input gate circuit. 1. A semiconductor integrated circuit comprising a pull-down or pull-up MOSFET provided in a hold mode, and a control signal for inhibiting input to the input gate circuit is applied to the gate of the high-voltage MOSFET in a hold mode.
JP1985102219U 1985-07-04 1985-07-04 Expired JPH0449706Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985102219U JPH0449706Y2 (en) 1985-07-04 1985-07-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985102219U JPH0449706Y2 (en) 1985-07-04 1985-07-04

Publications (2)

Publication Number Publication Date
JPS629825U true JPS629825U (en) 1987-01-21
JPH0449706Y2 JPH0449706Y2 (en) 1992-11-24

Family

ID=30973668

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985102219U Expired JPH0449706Y2 (en) 1985-07-04 1985-07-04

Country Status (1)

Country Link
JP (1) JPH0449706Y2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5781630A (en) * 1980-11-07 1982-05-21 Toshiba Corp Electronic circuit
JPS57190351A (en) * 1981-05-20 1982-11-22 Toshiba Corp Semiconductor integrated circuit device
JPS5815277A (en) * 1981-07-21 1983-01-28 Toshiba Corp Input protecting circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5781630A (en) * 1980-11-07 1982-05-21 Toshiba Corp Electronic circuit
JPS57190351A (en) * 1981-05-20 1982-11-22 Toshiba Corp Semiconductor integrated circuit device
JPS5815277A (en) * 1981-07-21 1983-01-28 Toshiba Corp Input protecting circuit

Also Published As

Publication number Publication date
JPH0449706Y2 (en) 1992-11-24

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