JPS61195126U - - Google Patents
Info
- Publication number
- JPS61195126U JPS61195126U JP5904285U JP5904285U JPS61195126U JP S61195126 U JPS61195126 U JP S61195126U JP 5904285 U JP5904285 U JP 5904285U JP 5904285 U JP5904285 U JP 5904285U JP S61195126 U JPS61195126 U JP S61195126U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- control signal
- gate electrode
- channel
- channel mosfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 3
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Electronic Switches (AREA)
Description
第１図は本考案の実施例を示す回路図、第２図
は第１図に示された実施例の動作を示す波形図、
第３図は従来例を示す回路図、第４図は第３図の
動作を示す波形図である。
主な図番の説明、４，１０……トランスミツシ
ヨンゲート、７，８，９，１１……インバータ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of the embodiment shown in FIG. 1,
FIG. 3 is a circuit diagram showing a conventional example, and FIG. 4 is a waveform diagram showing the operation of FIG. 3. Explanation of main drawing numbers: 4, 10...transmission gate, 7, 8, 9, 11...inverter.
Claims (1)
いはアナログスイツチ等を構成するＮチヤンネル
ＭＯＳＦＥＴ及びＰチヤンネルＭＯＳＦＥＴと、
該ＮチヤンネルＭＯＳＦＥＴのゲート電極とＰチ
ヤンネルＭＯＳＦＥＴのゲート電極に互いに逆相
の制御信号を印加するために一方の制御信号線に
挿入された反転素子とを少なくとも備えた半導体
装置に於いて、前記反転素子によつて遅延される
時間と略等しい遅延時間を有する遅延素子を他方
の制御信号に挿入したことを特徴とする半導体装
置。 N-channel MOSFETs and P-channel MOSFETs that are connected in parallel to form a transmission gate or analog switch, etc.;
In the semiconductor device, the semiconductor device includes at least an inverting element inserted into one control signal line for applying control signals of mutually opposite phases to the gate electrode of the N-channel MOSFET and the gate electrode of the P-channel MOSFET. A semiconductor device characterized in that a delay element having a delay time substantially equal to the time delayed by the element is inserted into the other control signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5904285U JPS61195126U (en) | 1985-04-19 | 1985-04-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5904285U JPS61195126U (en) | 1985-04-19 | 1985-04-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61195126U true JPS61195126U (en) | 1986-12-05 |
Family
ID=30585099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5904285U Pending JPS61195126U (en) | 1985-04-19 | 1985-04-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61195126U (en) |
-
1985
- 1985-04-19 JP JP5904285U patent/JPS61195126U/ja active Pending