JPS6249329U - - Google Patents
Info
- Publication number
- JPS6249329U JPS6249329U JP14214985U JP14214985U JPS6249329U JP S6249329 U JPS6249329 U JP S6249329U JP 14214985 U JP14214985 U JP 14214985U JP 14214985 U JP14214985 U JP 14214985U JP S6249329 U JPS6249329 U JP S6249329U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- push button
- button switches
- signals
- controlled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Electronic Switches (AREA)
Description
第１図は本考案の一実施例のブロツク図、第２
図は第１図の動作波形図、第３図は従来の押釦ス
イツチ制御回路を示す図、
第１図において、１，９……押釦スイツチ、２
，１０……入力端子、３，１１……ラツチ、４…
…加算ゲート回路、５，１５，１６…乗算ゲート
回路、６，１４……インバータ回路、７……タイ
マー回路、８，１７……出力端子、１２，１３…
…遅延回路、１８，１９……被制御機器。第３図
において、２１，２７……押釦スイツチ、２２，
２８……入力端子、２３，２９……積分回路、２
４，３５……遅延回路、２５，３１……出力端子
、２６，３２……被制御機器。
Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is an operation waveform diagram of Figure 1, and Figure 3 is a diagram showing a conventional push button switch control circuit.
, 10...input terminal, 3, 11...latch, 4...
... Addition gate circuit, 5, 15, 16 ... Multiplication gate circuit, 6, 14 ... Inverter circuit, 7 ... Timer circuit, 8, 17 ... Output terminal, 12, 13 ...
...Delay circuit, 18, 19... Controlled equipment. In FIG. 3, 21, 27...push button switch, 22,
28...Input terminal, 23, 29...Integrator circuit, 2
4, 35... Delay circuit, 25, 31... Output terminal, 26, 32... Controlled device.
Claims (1)
する回路と、記憶した信号の論理和によるタイミ
ングで動作する時計回路と、押釦スイツチを同時
に２個以上制御した時の優先回路とを具備するこ
とを特徴とする押釦スイツチ制御回路。 It is characterized by comprising a circuit that individually stores switch signals from the push button switches, a clock circuit that operates at timing based on the logical sum of the stored signals, and a priority circuit when two or more push button switches are controlled at the same time. Push button switch control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14214985U JPS6249329U (en) | 1985-09-17 | 1985-09-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14214985U JPS6249329U (en) | 1985-09-17 | 1985-09-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6249329U true JPS6249329U (en) | 1987-03-26 |
Family
ID=31050599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14214985U Pending JPS6249329U (en) | 1985-09-17 | 1985-09-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6249329U (en) |
-
1985
- 1985-09-17 JP JP14214985U patent/JPS6249329U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6249329U (en) | ||
| JPS5920732U (en) | timer circuit | |
| JPS6281240U (en) | ||
| JPS6033681U (en) | digital clock correction circuit | |
| JPS62177128U (en) | ||
| JPS61178498U (en) | ||
| JPS59162755U (en) | Alternate type switch | |
| JPS63185319U (en) | ||
| JPS61160530U (en) | ||
| JPS6296754U (en) | ||
| JPS62159027U (en) | ||
| JPS6217237U (en) | ||
| JPS60145392U (en) | Electronic clock with alarm function | |
| JPS58189629U (en) | Day reset circuit using analog switch | |
| JPS5950175U (en) | remote control unit | |
| JPS60129726U (en) | electronic timer | |
| JPS60100692U (en) | Electronic clock timing device | |
| JPH039043U (en) | ||
| JPS6447121U (en) | ||
| JPS58132434U (en) | Chattering absorption circuit | |
| JPS58183797U (en) | Automatic flasher with timer | |
| JPS6222584U (en) | ||
| JPS6197231U (en) | ||
| JPS61195126U (en) | ||
| JPS61119791U (en) |