JPS58189629U - Day reset circuit using analog switch - Google Patents

Day reset circuit using analog switch

Info

Publication number
JPS58189629U
JPS58189629U JP8703482U JP8703482U JPS58189629U JP S58189629 U JPS58189629 U JP S58189629U JP 8703482 U JP8703482 U JP 8703482U JP 8703482 U JP8703482 U JP 8703482U JP S58189629 U JPS58189629 U JP S58189629U
Authority
JP
Japan
Prior art keywords
analog switch
reset circuit
day
day reset
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8703482U
Other languages
Japanese (ja)
Inventor
正男 吉田
Original Assignee
パイオニア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パイオニア株式会社 filed Critical パイオニア株式会社
Priority to JP8703482U priority Critical patent/JPS58189629U/en
Publication of JPS58189629U publication Critical patent/JPS58189629U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のアナログスイッチの使用例をガす回路図
、第2図はこの考案のアナログスイッチを用いたデイグ
リッジャ回路の一実施例を示す回ρ  略図、第3図は
この考案のアナログスイッチを用−いたデイグリッジャ
回路の他の実施例におけるア:  ナログスイッチの接
続状態を示す回路図、第4図1  はこの考案のアナロ
グスイッチを用いたディグリッジャ回路のさらに異なる
他の実施例を示す回路図である。 e    113〜I IC,1,2a〜12b、  
13a〜13b=  ・・・・・・アナログスイッチ、
14・・・・・・D/Aコンバータ。
Fig. 1 is a circuit diagram showing an example of the use of a conventional analog switch, Fig. 2 is a circuit diagram showing an example of a day glitch circuit using the analog switch of this invention, and Fig. 3 is a circuit diagram of an analog switch of this invention. A: A circuit diagram showing the connection state of the analog switch in another embodiment of the deglidger circuit using the analog switch of this invention. It is. e 113~I IC, 1, 2a~12b,
13a to 13b= ...analog switch,
14...D/A converter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 所定の系ごとに複数個の・アナログスイッチを立列に接
続し、各アナログスイッチのゲートを同一のスイッチン
グパルスによってオン、オフさせ父なるアナログスイッ
チを用いたデイグリツジャ匡路。
This is a day-grid switch that connects multiple analog switches in series for each given system and turns on and off the gates of each analog switch using the same switching pulse.
JP8703482U 1982-06-11 1982-06-11 Day reset circuit using analog switch Pending JPS58189629U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8703482U JPS58189629U (en) 1982-06-11 1982-06-11 Day reset circuit using analog switch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8703482U JPS58189629U (en) 1982-06-11 1982-06-11 Day reset circuit using analog switch

Publications (1)

Publication Number Publication Date
JPS58189629U true JPS58189629U (en) 1983-12-16

Family

ID=30095785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8703482U Pending JPS58189629U (en) 1982-06-11 1982-06-11 Day reset circuit using analog switch

Country Status (1)

Country Link
JP (1) JPS58189629U (en)

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