JPS6219827U - - Google Patents

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Publication number
JPS6219827U
JPS6219827U JP11136385U JP11136385U JPS6219827U JP S6219827 U JPS6219827 U JP S6219827U JP 11136385 U JP11136385 U JP 11136385U JP 11136385 U JP11136385 U JP 11136385U JP S6219827 U JPS6219827 U JP S6219827U
Authority
JP
Japan
Prior art keywords
logic gate
circuit
gate
input signal
inputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11136385U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11136385U priority Critical patent/JPS6219827U/ja
Publication of JPS6219827U publication Critical patent/JPS6219827U/ja
Pending legal-status Critical Current

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  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例を示す回路図、第2図
は本考案の他の実施例を示す回路図、第3図は従
来例を示す回路図である。 主な図番の説明、7,8,9……入力端、10
……出力端、11,12……伝送MOSFET、
13……NANDゲート、17……MOSFET
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the present invention, and FIG. 3 is a circuit diagram showing a conventional example. Explanation of main drawing numbers, 7, 8, 9...Input terminal, 10
...Output end, 11, 12...Transmission MOSFET,
13...NAND gate, 17...MOSFET
.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数の入力を有する論理ゲート回路に於いて、
前記複数の入力の中で最も遅く到来する信号が印
加される入力端と出力端との間にソースードレイ
ンパスが介在し、ゲート電極に他の入力信号が印
加された伝送MOSFETと、前記他の入力信号
が印加された反転論理ゲート(インバータあるい
はNANDゲート)と、該反転論理ゲートの出力
がゲート電極に印加され、前記出力端と所定電位
との間に介在されたMOSFETとから成る論理
ゲート回路。
In a logic gate circuit with multiple inputs,
A transmission MOSFET in which a source-drain path is interposed between an input terminal to which a signal arriving latest among the plurality of inputs is applied and an output terminal, and another input signal is applied to a gate electrode; A logic gate consisting of an inverting logic gate (an inverter or a NAND gate) to which an input signal of circuit.
JP11136385U 1985-07-19 1985-07-19 Pending JPS6219827U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11136385U JPS6219827U (en) 1985-07-19 1985-07-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11136385U JPS6219827U (en) 1985-07-19 1985-07-19

Publications (1)

Publication Number Publication Date
JPS6219827U true JPS6219827U (en) 1987-02-05

Family

ID=30991217

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11136385U Pending JPS6219827U (en) 1985-07-19 1985-07-19

Country Status (1)

Country Link
JP (1) JPS6219827U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57109427A (en) * 1980-12-26 1982-07-07 Toshiba Corp Semiconductor integrated circuit device
JPS57157639A (en) * 1981-03-24 1982-09-29 Toshiba Corp Semiconductor circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57109427A (en) * 1980-12-26 1982-07-07 Toshiba Corp Semiconductor integrated circuit device
JPS57157639A (en) * 1981-03-24 1982-09-29 Toshiba Corp Semiconductor circuit

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