JPS61103931U - - Google Patents
Info
- Publication number
- JPS61103931U JPS61103931U JP18798084U JP18798084U JPS61103931U JP S61103931 U JPS61103931 U JP S61103931U JP 18798084 U JP18798084 U JP 18798084U JP 18798084 U JP18798084 U JP 18798084U JP S61103931 U JPS61103931 U JP S61103931U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- gate
- gate circuit
- timer
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Electronic Switches (AREA)
Description
第１図及び第２図は本考案に係るタイマ回路の
第１、第２実施例の回路図、第３図は従来のタイ
マ回路の回路図である。
１…ワンタツチスイツチ、２…微分回路、３〜
６…ノアゲート回路、７…タイマ回路本体部、８
，９…第１、第２の遅延回路。
1 and 2 are circuit diagrams of first and second embodiments of a timer circuit according to the present invention, and FIG. 3 is a circuit diagram of a conventional timer circuit. 1...One-touch switch, 2...Differential circuit, 3~
6... Noah gate circuit, 7... timer circuit main body, 8
, 9...first and second delay circuits.
Claims (1)
と、第１〜第４のノアゲート回路と、第１、第２
の遅延回路と、ＣＲタイマ回路本体部とを備え、
前記ワンタツチスイツチは前記微分回路を介して
前記第１、第２のノアゲート回路の入力端に接続
され、前記第１のノアゲート回路の出力端は前記
第３のノアゲート回路の入力端に接続され、前記
第２のノアゲート回路の出力端は前記第４のノア
ゲート回路の入力端に接続され、前記第３のノア
ゲート回路の出力端はタイマ出力端と前記第４の
ノアゲート回路の入力端と前記第２のノアゲート
回路の入力端とにそれぞれ接続され、前記第４の
ノアゲート回路の出力端は前記タイマ回路本体部
の入力端と前記第３のノアゲート回路の入力端と
前記第１のノアゲート回路の入力端とにそれぞれ
接続され、前記タイマ回路本体部の出力端は前記
第４のノアゲート回路の入力端に接続され、前記
第１の遅延回路は前記第４のノアゲート回路の出
力端から前記第１のノアゲート回路の入力端に至
る線路に接続され、前記第２の遅延回路は前記第
３のノアゲート回路の出力端から前記第２のノア
ゲート回路の入力端に至る線路に接続されている
ことを特徴とするタイマ回路。 A self-resetting one-touch switch, a differential circuit, first to fourth NOR gate circuits, and first and second
a delay circuit and a CR timer circuit main body,
The one-touch switch is connected to the input terminals of the first and second NOR gate circuits via the differentiating circuit, and the output terminal of the first NOR gate circuit is connected to the input terminal of the third NOR gate circuit, The output terminal of the second NOR gate circuit is connected to the input terminal of the fourth NOR gate circuit, and the output terminal of the third NOR gate circuit is connected to the timer output terminal, the input terminal of the fourth NOR gate circuit, and the second NOR gate circuit. The output terminal of the fourth NOR gate circuit is connected to the input terminal of the timer circuit main body, the input terminal of the third NOR gate circuit, and the input terminal of the first NOR gate circuit. The output end of the timer circuit main body is connected to the input end of the fourth NOR gate circuit, and the first delay circuit connects the output end of the fourth NOR gate circuit to the first NOR gate. The second delay circuit is connected to a line leading to an input end of the circuit, and the second delay circuit is connected to a line leading from an output end of the third NOR gate circuit to an input end of the second NOR gate circuit. timer circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18798084U JPS61103931U (en) | 1984-12-11 | 1984-12-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18798084U JPS61103931U (en) | 1984-12-11 | 1984-12-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61103931U true JPS61103931U (en) | 1986-07-02 |
Family
ID=30745452
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18798084U Pending JPS61103931U (en) | 1984-12-11 | 1984-12-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61103931U (en) |
-
1984
- 1984-12-11 JP JP18798084U patent/JPS61103931U/ja active Pending