JPS62191300U - - Google Patents
Info
- Publication number
- JPS62191300U JPS62191300U JP7978986U JP7978986U JPS62191300U JP S62191300 U JPS62191300 U JP S62191300U JP 7978986 U JP7978986 U JP 7978986U JP 7978986 U JP7978986 U JP 7978986U JP S62191300 U JPS62191300 U JP S62191300U
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- output
- output terminal
- resistors
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 3
Description
第１図は本考案のモード切換回路の構成を示す
図、第２図は同、他の実施例の構成を示す図、第
３図および第４図は従来のモード切換回路の構成
を示す図である。
１，２……第１、第２の増幅器、３，４……第
１、第２の入力端子、１３，１４，１５，１６…
…第１、第２、第３、第４の出力端子、１７，１
８，１９，２０……第１、第２、第３、第４の抵
抗、２１，２２……第１、第２のスイツチ。
FIG. 1 is a diagram showing the configuration of a mode switching circuit according to the present invention, FIG. 2 is a diagram showing the configuration of another embodiment of the same, and FIGS. 3 and 4 are diagrams showing the configuration of a conventional mode switching circuit. It is. 1, 2...first and second amplifiers, 3,4...first and second input terminals, 13,14,15,16...
...First, second, third, fourth output terminals, 17, 1
8, 19, 20...first, second, third, fourth resistors, 21,22...first, second switches.
Claims (1)
記第１の増幅器１の出力を第１、第２の抵抗１７
，１８を介して第１、第２の出力端子１３，１４
にそれぞれ接続し、上記第２の増幅器２の出力を
第３、第４の抵抗１９，２０を介して第３、第４
の出力端子１５，１６にそれぞれ接続し、上記第
１の出力端子１３と第３の出力端子１５との間を
第１のスイツチ２１を介して接続するとともに、
上記第２の出力端子１４と第４の出力端子１６と
の間を第２のスイツチ２２を介して接続したこと
を特徴とするモード切換回路。 A first amplifier 1 and a second amplifier 2 are provided, and the output of the first amplifier 1 is connected to the first and second resistors 17.
, 18 to the first and second output terminals 13, 14.
The output of the second amplifier 2 is connected to the third and fourth resistors 19 and 20 through the third and fourth resistors 19 and 20, respectively.
and connecting the first output terminal 13 and the third output terminal 15 via the first switch 21, respectively.
A mode switching circuit characterized in that the second output terminal 14 and the fourth output terminal 16 are connected via a second switch 22.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7978986U JPH033039Y2 (en) | 1986-05-27 | 1986-05-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7978986U JPH033039Y2 (en) | 1986-05-27 | 1986-05-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62191300U true JPS62191300U (en) | 1987-12-05 |
| JPH033039Y2 JPH033039Y2 (en) | 1991-01-25 |
Family
ID=30929984
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7978986U Expired JPH033039Y2 (en) | 1986-05-27 | 1986-05-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH033039Y2 (en) |
-
1986
- 1986-05-27 JP JP7978986U patent/JPH033039Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH033039Y2 (en) | 1991-01-25 |