JPH0438120U - - Google Patents
Info
- Publication number
- JPH0438120U JPH0438120U JP7933490U JP7933490U JPH0438120U JP H0438120 U JPH0438120 U JP H0438120U JP 7933490 U JP7933490 U JP 7933490U JP 7933490 U JP7933490 U JP 7933490U JP H0438120 U JPH0438120 U JP H0438120U
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- switch
- power amplifier
- resistor
- amplifies
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005236 sound signal Effects 0.000 claims 2
- 230000003321 amplification Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Amplifiers (AREA)
Description
第１図はこの考案に係る増幅回路の実施例を示
す回路図、第２図は従来の実施例を示す回路図で
ある。
主な符号の説明、１……第１の入力端、２……
第１の電力増幅器、３……第２の入力端、４……
第２の電力増幅器、４ｂ……反転入力端子、４ｃ
……同相入力端子、５ａ……第１のスイツチ、５
ｂ……第２のスイツチ、６……抵抗器。
FIG. 1 is a circuit diagram showing an embodiment of an amplifier circuit according to this invention, and FIG. 2 is a circuit diagram showing a conventional embodiment. Explanation of main symbols, 1...first input terminal, 2...
First power amplifier, 3... Second input terminal, 4...
Second power amplifier, 4b...inverting input terminal, 4c
...In-phase input terminal, 5a...First switch, 5
b...Second switch, 6...Resistor.
Claims (1)
入力端の音声信号を増幅する第１の電力増幅器と
、前記第２の入力端の音声信号を増幅する第２の
電力増幅器と、第１のスイツチと、前記第１のス
イツチに連動する第２のスイツチとからなり、前
記第１のスイツチ及び第２のスイツチが共に第１
の位置にある時、前記第２の電力増幅器の反転入
力端子を抵抗器を介して前記第２の入力端に接続
せしめると共に前記第２の電力増幅器の同相入力
端子をグランドに接続せしめ、また、第１のスイ
ツチ及び第２のスイツチが第２の位置にある時、
前記第２の電力増幅器の反転入力端子を抵抗器を
介してグランドに接続せしめると共に前記第２の
電力増幅器の同相入力端子を前記第１の入力端に
接続せしめるように構成したことを特徴とする増
幅回路。 a first input terminal, a second input terminal, a first power amplifier that amplifies the audio signal at the first input terminal, and a second power amplifier that amplifies the audio signal at the second input terminal. , a first switch, and a second switch that is linked to the first switch, and both the first switch and the second switch are connected to the first switch.
, the inverting input terminal of the second power amplifier is connected to the second input terminal via a resistor, and the in-phase input terminal of the second power amplifier is connected to ground, and When the first switch and the second switch are in the second position,
The inverting input terminal of the second power amplifier is connected to ground via a resistor, and the in-phase input terminal of the second power amplifier is connected to the first input terminal. Amplification circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7933490U JPH0438120U (en) | 1990-07-27 | 1990-07-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7933490U JPH0438120U (en) | 1990-07-27 | 1990-07-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0438120U true JPH0438120U (en) | 1992-03-31 |
Family
ID=31623400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7933490U Pending JPH0438120U (en) | 1990-07-27 | 1990-07-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0438120U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014099809A (en) * | 2012-11-15 | 2014-05-29 | Asahi Kasei Electronics Co Ltd | Buffer circuit |
-
1990
- 1990-07-27 JP JP7933490U patent/JPH0438120U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014099809A (en) * | 2012-11-15 | 2014-05-29 | Asahi Kasei Electronics Co Ltd | Buffer circuit |