JPS61134112U - - Google Patents
Info
- Publication number
- JPS61134112U JPS61134112U JP1622285U JP1622285U JPS61134112U JP S61134112 U JPS61134112 U JP S61134112U JP 1622285 U JP1622285 U JP 1622285U JP 1622285 U JP1622285 U JP 1622285U JP S61134112 U JPS61134112 U JP S61134112U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- power amplifier
- amplifier circuit
- power amplification
- amplifies
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 230000003321 amplification Effects 0.000 claims 3
- 238000003199 nucleic acid amplification method Methods 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Amplifiers (AREA)
Description
第１図は本考案の一実施例によるＢＴＬ電力増
幅回路の回路図、第２図は従来のＢＴＬ電力増幅
回路の回路図である。
１……第１電力増幅回路、２……第２の電力増
幅回路、３……第１の電力増幅回路の出力端子、
４……第２の電力増幅回路の出力端子、５……負
荷、６，７……信号分割用抵抗、８……第２の電
力増幅回路の反転入力端子、９……コンデンサ。
FIG. 1 is a circuit diagram of a BTL power amplifier circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional BTL power amplifier circuit. 1... First power amplifier circuit, 2... Second power amplifier circuit, 3... Output terminal of the first power amplifier circuit,
4... Output terminal of the second power amplifier circuit, 5... Load, 6, 7... Resistor for signal division, 8... Inverting input terminal of the second power amplifier circuit, 9... Capacitor.
Claims (1)
第１の電力増幅回路の出力端子と基準電位間に接
続されたコンデンサと少くとも２個の抵抗の直列
回路と、該抵抗の中間接続点の信号を前記第１の
電力増幅回路とは逆位相で増幅する第２の電力増
幅回路と、前記第１および第２の電力増幅回路の
出力端子間に接続された負荷とを有することを特
徴とするＢＴＬ電力増幅回路。 a first power amplifier circuit that amplifies an input signal; a series circuit of a capacitor and at least two resistors connected between the output terminal of the first power amplifier circuit and a reference potential; and an intermediate connection point between the resistors. a second power amplification circuit that amplifies the signal in a phase opposite to that of the first power amplification circuit, and a load connected between the output terminals of the first and second power amplification circuits. BTL power amplifier circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1622285U JPS61134112U (en) | 1985-02-07 | 1985-02-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1622285U JPS61134112U (en) | 1985-02-07 | 1985-02-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61134112U true JPS61134112U (en) | 1986-08-21 |
Family
ID=30502789
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1622285U Pending JPS61134112U (en) | 1985-02-07 | 1985-02-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61134112U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5849193B2 (en) * | 1977-05-09 | 1983-11-02 | 富士通株式会社 | Hammering control method in serial printers |
-
1985
- 1985-02-07 JP JP1622285U patent/JPS61134112U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5849193B2 (en) * | 1977-05-09 | 1983-11-02 | 富士通株式会社 | Hammering control method in serial printers |
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