JPS635716U

JPS635716U -

Info

Publication number: JPS635716U
Application number: JP9947386U
Authority: JP
Priority date: 1986-06-27
Filing date: 1986-06-27
Publication date: 1988-01-14
Anticipated expiration: 2001-06-27
Also published as: JPH062334Y2

Description

[Brief explanation of the drawing]

第１図は本考案の平衡増幅器の構成を示す図、
第２図は同、他の実施例の構成を示す図、第３図
は従来の平衡増幅器の構成を示す図である。１……第１の入力抵抗、２……第１の差動型増
幅器、３……第１の出力端子、４……第１の帰還
抵抗、５……第２の入力抵抗、６……第２の差動
型増幅器、７……第２の出力端子、８……第２の
帰還抵抗、９……電源回路、１０……第１のミラ
ー積分回路、１１……第１の積分抵抗、１２……
第１の積分コンデンサ、１３……第３の差動型増
幅器、１４，１５……正、負の電源供給端子、１
６……第１の抵抗、１７……第２の抵抗、１８…
…第３の抵抗、１９……第４の抵抗、２０……第
２のミラー積分回路、２１……第２の積分抵抗、
２２……第２の積分コンデンサ、２３……第４の
差動型増幅器、２４……第５の抵抗、２５……第
６の抵抗。 FIG. 1 is a diagram showing the configuration of the balanced amplifier of the present invention,
FIG. 2 is a diagram showing the configuration of another embodiment of the same, and FIG. 3 is a diagram showing the configuration of a conventional balanced amplifier. DESCRIPTION OF SYMBOLS 1... First input resistance, 2... First differential amplifier, 3... First output terminal, 4... First feedback resistor, 5... Second input resistor, 6... Second differential amplifier, 7... Second output terminal, 8... Second feedback resistor, 9... Power supply circuit, 10... First Miller integrating circuit, 11... First integrating resistor , 12...
First integrating capacitor, 13...Third differential amplifier, 14, 15...Positive and negative power supply terminals, 1
6...first resistor, 17...second resistor, 18...
...Third resistor, 19... Fourth resistor, 20... Second Miller integrating circuit, 21... Second integrating resistor,
22... Second integrating capacitor, 23... Fourth differential amplifier, 24... Fifth resistor, 25... Sixth resistor.

Claims

[Scope of utility model registration request]

a first amplifier 2 that amplifies a first input;
a second amplifier 6 for amplifying the input of the first amplifier 2, and an output is taken out between the first output terminal 3 of the first amplifier 2 and the second output terminal 7 of the second amplifier 6. In the balanced amplifier, the first output terminal 3 is connected to the inverting input terminal of the third differential amplifier 13 via the first integrating resistor 11, and the inverting input terminal is connected to the first integrating capacitor 12. The first Miller integration circuit is connected to the output of the third differential amplifier 13 through the third differential amplifier 13 and supplies a voltage obtained by equally dividing the power supply voltage to the non-inverting input terminal of the third differential amplifier 13. 10, and provides negative feedback to the input side of the first differential amplifier 2 of the very low frequency component below a predetermined frequency and the DC component detected and amplified by the first Miller integrating circuit 10. constitutes a first amplification type negative feedback loop, and connects the second output terminal 7 to the inverting input terminal of the fourth differential amplifier 23 via the second integrating resistor 21, and connects the second output terminal 7 to the inverting input terminal of the fourth differential amplifier 23. is connected to the output of the fourth differential amplifier 23 via the second integrating capacitor 22, and a voltage obtained by equally dividing the power supply voltage is supplied to the non-inverting input terminal of the fourth differential amplifier 23. and second
A mirror integrating circuit 20 is configured, and the very low frequency components below a predetermined frequency and the DC component detected and amplified by the second mirror integrating circuit 20 are sent to the input side of the second differential amplifier 6. Leave a negative feedback to the second
A balanced amplifier characterized by comprising an amplification type negative feedback loop.