JPH0390118U - - Google Patents

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Publication number
JPH0390118U
JPH0390118U JP14934289U JP14934289U JPH0390118U JP H0390118 U JPH0390118 U JP H0390118U JP 14934289 U JP14934289 U JP 14934289U JP 14934289 U JP14934289 U JP 14934289U JP H0390118 U JPH0390118 U JP H0390118U
Authority
JP
Japan
Prior art keywords
resistor
input
collector
power supply
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14934289U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14934289U priority Critical patent/JPH0390118U/ja
Publication of JPH0390118U publication Critical patent/JPH0390118U/ja
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の実施例の回路図、第2図は第
1図の等価回路を示した図、第3図は差動増幅回
路の基本的な例を示す回路図。 図中、e,e……それぞれ、第1、第2の
入力、−V,+V……それぞれ、第1、第2の電
源、VOUT……差動増幅出力。
FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a diagram showing an equivalent circuit of FIG. 1, and FIG. 3 is a circuit diagram showing a basic example of a differential amplifier circuit. In the figure, e1 , e2 ...first and second inputs, respectively, -V, +V...first and second power supplies, respectively, VOUT...differential amplification output.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] トランジスタのベースに第1の入力を、エミツ
タには第1の抵抗器を介して第2の入力をそれぞ
れ接続し、前記ベースにはまたバイアス用の第2
の抵抗器を接続し、前記第1の抵抗器における前
記第2の入力側と第1の電源との間には前記第2
の抵抗器と同じ抵抗値を有する第3の抵抗器を接
続し、コレクタには第4の抵抗器を介して第2の
電源を接続し、該コレクタより差動増幅出力を取
り出すようにしたことを特徴とする差動増幅回路
A first input is connected to the base of the transistor, a second input is connected to the emitter via a first resistor, and a second input for biasing is connected to the base.
A resistor is connected between the second input side of the first resistor and the first power supply.
A third resistor having the same resistance value as the resistor is connected, the second power supply is connected to the collector through the fourth resistor, and the differential amplified output is taken out from the collector. A differential amplifier circuit featuring:
JP14934289U 1989-12-27 1989-12-27 Pending JPH0390118U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14934289U JPH0390118U (en) 1989-12-27 1989-12-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14934289U JPH0390118U (en) 1989-12-27 1989-12-27

Publications (1)

Publication Number Publication Date
JPH0390118U true JPH0390118U (en) 1991-09-13

Family

ID=31695746

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14934289U Pending JPH0390118U (en) 1989-12-27 1989-12-27

Country Status (1)

Country Link
JP (1) JPH0390118U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012521666A (en) * 2009-03-19 2012-09-13 クゥアルコム・インコーポレイテッド Common gate common source amplifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012521666A (en) * 2009-03-19 2012-09-13 クゥアルコム・インコーポレイテッド Common gate common source amplifier

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