JPS6188335U - - Google Patents

Info

Publication number
JPS6188335U
JPS6188335U JP17371584U JP17371584U JPS6188335U JP S6188335 U JPS6188335 U JP S6188335U JP 17371584 U JP17371584 U JP 17371584U JP 17371584 U JP17371584 U JP 17371584U JP S6188335 U JPS6188335 U JP S6188335U
Authority
JP
Japan
Prior art keywords
circuit
cmos inverter
resistor
stages
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17371584U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17371584U priority Critical patent/JPS6188335U/ja
Publication of JPS6188335U publication Critical patent/JPS6188335U/ja
Pending legal-status Critical Current

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  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図は本考案の実施例を、第3
図は従来例をそれぞれ示し、第1図はシユミツト
回路の具体的な回路構成図、第2図は同回路の動
作を説明するためのタイムチヤート、第3図はシ
ユミツト回路の回路構成図である。 1…シユミツト回路、2,4,6…CMOSインバ
ータ回路、2a,4a,6a…電源入力端子、2
b,4b,6b…アース端子、R1…抵抗。
Figures 1 and 2 show an embodiment of the present invention;
The figures show conventional examples, and Fig. 1 is a specific circuit diagram of a Schmitt circuit, Fig. 2 is a time chart for explaining the operation of the circuit, and Fig. 3 is a circuit diagram of a Schmitt circuit. . 1... Schmitt circuit, 2, 4, 6... CMOS inverter circuit, 2a, 4a, 6a... power input terminal, 2
b, 4b, 6b...earth terminal, R1...resistance.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 少なくとも3段のCMOSインバータ回路を備え、
各CMOSインバータ回路はその入出力部を介して縦
接接続されるとともに、各回路のアース端子は互
いに共通に接続され、該共通接続部は抵抗を介し
て接地されていることを特徴とするシユミツト回
路。
Equipped with at least three stages of CMOS inverter circuits,
Each CMOS inverter circuit is vertically connected via its input/output section, and the ground terminals of each circuit are commonly connected to each other, and the common connection is grounded via a resistor. circuit.
JP17371584U 1984-11-15 1984-11-15 Pending JPS6188335U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17371584U JPS6188335U (en) 1984-11-15 1984-11-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17371584U JPS6188335U (en) 1984-11-15 1984-11-15

Publications (1)

Publication Number Publication Date
JPS6188335U true JPS6188335U (en) 1986-06-09

Family

ID=30731356

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17371584U Pending JPS6188335U (en) 1984-11-15 1984-11-15

Country Status (1)

Country Link
JP (1) JPS6188335U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50116161A (en) * 1974-02-25 1975-09-11

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50116161A (en) * 1974-02-25 1975-09-11

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