JPS62183424U - - Google Patents
Info
- Publication number
- JPS62183424U JPS62183424U JP7153586U JP7153586U JPS62183424U JP S62183424 U JPS62183424 U JP S62183424U JP 7153586 U JP7153586 U JP 7153586U JP 7153586 U JP7153586 U JP 7153586U JP S62183424 U JPS62183424 U JP S62183424U
- Authority
- JP
- Japan
- Prior art keywords
- delay line
- variable delay
- line element
- movable contact
- switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案に係る可変遅延線の一実施例を
応用例とともに示す回路図、第２図は第１図に示
す第１の可変遅延線素子の具体的構成を示す部分
斜視図、第３図および第４図は第１図に示す第２
の可変遅延線素子の具体的構成を示す正面図およ
び側面図、第５図および第６図は本考案の他の実
施例を応用例とともに示す回路図である。
ＤＬ１…第１の可変遅延線素子、ＤＬ２…第２
の可変遅延線素子、ＤＬ３…固定遅延線素子、１
，１５…可動接点、１１，１３…固定接点、Ａｎ
，Ｂｎ…切り換え手段（２入力ＡＮＤゲート）、
Ｃｎ…切り換え手段（２入力ＮＯＲゲート）、Ｉ
…切り換え手段（インバータ）、Ｐ１…入力端（
一端）、Ｐ２，Ｐ４…他端。
1 is a circuit diagram showing an embodiment of a variable delay line according to the present invention together with an application example; FIG. 2 is a partial perspective view showing a specific configuration of the first variable delay line element shown in FIG. 1; Figures 3 and 4 show the second part shown in Figure 1.
FIGS. 5 and 6 are circuit diagrams showing other embodiments of the present invention along with application examples. DL1...first variable delay line element, DL2...second
variable delay line element, DL3...Fixed delay line element, 1
, 15... Movable contact, 11, 13... Fixed contact, An
, Bn...switching means (2-input AND gate),
Cn...Switching means (2-input NOR gate), I
...Switching means (inverter), P1 ...Input end (
one end), P 2 , P 4 ...the other end.
Claims (1)
可動接点を有し一端を入力端とした第１の可変遅
延線素子と、 前記固定接点の切り換えで得られる遅延時間ス
テツプより大きな遅延時間ステツプで形成された
複数の固定接点およびこれらの固定接点を切り換
える可動接点とを有し、この可動接点が前記第１
の可変遅延線素子の他端に接続され、かつ一端が
終端された第２の可変遅延線素子と、 前記第１の可変遅延線素子の可動接点からの信
号出力と、前記第２の可変遅延線素子の他端から
の信号出力を切り換えてそれらの遅延時間差信号
を出力する切り換え手段と、 を具備してなることを特徴とする可変遅延線。 (2) 前記切り換え手段が電子的切り換え手段で
ある実用新案登録請求の範囲第１項記載の可変遅
延線。 (3) 前記第２の可変遅延線素子が、固定遅延線
素子を介して前記第１の可変遅延線素子に接続さ
れてなる実用新案登録請求の範囲第１項もしくは
第２項記載の可変遅延線。 (4) 前記第２の可変遅延線素子が、固定遅延線
素子を介して前記切り換え手段に接続されてなる
実用新案登録請求の範囲第１項もしくは第２項記
載の可変遅延線。[Claims for Utility Model Registration] (1) A first variable delay line element having a plurality of fixed contacts and a movable contact for switching between them, one end of which is an input end, and a delay time step obtained by switching the fixed contacts. It has a plurality of fixed contacts formed with larger delay time steps and a movable contact for switching these fixed contacts, and this movable contact is connected to the first
a second variable delay line element connected to the other end of the variable delay line element and having one end terminated; a signal output from a movable contact of the first variable delay line element; and a signal output from the movable contact of the first variable delay line element; A variable delay line comprising: switching means for switching the signal output from the other end of the line element and outputting a delay time difference signal thereof; (2) The variable delay line according to claim 1, wherein the switching means is an electronic switching means. (3) The variable delay according to claim 1 or 2, wherein the second variable delay line element is connected to the first variable delay line element via a fixed delay line element. line. (4) The variable delay line according to claim 1 or 2, wherein the second variable delay line element is connected to the switching means via a fixed delay line element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7153586U JPS62183424U (en) | 1986-05-13 | 1986-05-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7153586U JPS62183424U (en) | 1986-05-13 | 1986-05-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62183424U true JPS62183424U (en) | 1987-11-20 |
Family
ID=30914176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7153586U Pending JPS62183424U (en) | 1986-05-13 | 1986-05-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62183424U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5524832B2 (en) * | 1975-07-08 | 1980-07-01 | ||
| JPS6128212A (en) * | 1984-07-17 | 1986-02-07 | Mitsubishi Electric Corp | Signal delay device |
-
1986
- 1986-05-13 JP JP7153586U patent/JPS62183424U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5524832B2 (en) * | 1975-07-08 | 1980-07-01 | ||
| JPS6128212A (en) * | 1984-07-17 | 1986-02-07 | Mitsubishi Electric Corp | Signal delay device |
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