JPS6168507U - - Google Patents
Info
- Publication number
- JPS6168507U JPS6168507U JP15351284U JP15351284U JPS6168507U JP S6168507 U JPS6168507 U JP S6168507U JP 15351284 U JP15351284 U JP 15351284U JP 15351284 U JP15351284 U JP 15351284U JP S6168507 U JPS6168507 U JP S6168507U
- Authority
- JP
- Japan
- Prior art keywords
- line
- point
- circuit pattern
- utility
- model registration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005452 bending Methods 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Pulse Circuits (AREA)
Description
第１図は本考案の可変遅延線の一実施例を示す
正面図、第２図は第１図の可変遅延線を用いた応
用例を示す回路図である。
１…回路パターン、３…入力点、５…折れ曲が
り線路、７…折り曲がり線路の導線路、９…第１
の折り曲げ部、１１…接続部材（接続片）、１２
…接続点、１３…第２の折り曲げ部、１５…短絡
部材（短絡片）、１７…第１の出力点、１９…第
２の出力点。
FIG. 1 is a front view showing an embodiment of the variable delay line of the present invention, and FIG. 2 is a circuit diagram showing an application example using the variable delay line of FIG. DESCRIPTION OF SYMBOLS 1...Circuit pattern, 3...Input point, 5...Bending line, 7...Conducting path of the bending line, 9...First
Bending portion, 11... Connection member (connection piece), 12
...Connection point, 13...Second bent portion, 15...Short circuit member (short circuit piece), 17...First output point, 19...Second output point.
Claims (1)
り線路と、 移動可能に配置されかつ前記回路パターンおよ
び前記折れ曲がり線路の導線路間を接続する接続
部材と、 移動可能に配置されかつ前記折れ曲がり線路に
あつて折り曲げ部の前後の前記導線路間を短絡す
る短絡部材と、 を具備してなることを特徴とする可変遅延線。 (2) 折れ曲がり線路の導線路における接続部材
との接続点から一方の端部側に出力点を形成する
とともに、この出力点に固定遅延線を縦続接続し
てなる実用新案登録請求の範囲第１項記載の可変
遅延線。 (3) 折れ曲がり線路の導線路における接続部材
との接続点から一方の端部側に第１の出力点を形
成するとともに前記接続点から他方の側に第２の
出力点を形成し、この第２の出力点に固定遅延線
を縦続接続してなる実用新案登録請求の範囲第１
項記載の可変遅延線。[Claims for Utility Model Registration] (1) A circuit pattern, a bent line arranged along the circuit pattern, and a connecting member that is movably arranged and connects the conductor lines of the circuit pattern and the bent line. A variable delay line comprising: a short-circuiting member that is movably arranged and that short-circuits between the conducting lines before and after the bending part in the bending line. (2) Utility model registration claim 1 in which an output point is formed on one end side from the connection point with the connecting member in the conductor line of the bent line, and a fixed delay line is cascaded to this output point. Variable delay line as described in section. (3) A first output point is formed on one end side from the connection point with the connection member in the conducting path of the bent line, and a second output point is formed on the other side from the connection point, and this Utility model registration claim 1 consisting of fixed delay lines connected in cascade to the output points of 2
Variable delay line as described in section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15351284U JPS6168507U (en) | 1984-10-09 | 1984-10-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15351284U JPS6168507U (en) | 1984-10-09 | 1984-10-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6168507U true JPS6168507U (en) | 1986-05-10 |
Family
ID=30711528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15351284U Pending JPS6168507U (en) | 1984-10-09 | 1984-10-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6168507U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010135869A (en) * | 2008-12-02 | 2010-06-17 | Kyocera Mita Corp | Wiring substrate, image forming apparatus, and wiring method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5040477A (en) * | 1973-08-07 | 1975-04-14 | ||
| JPS5374863A (en) * | 1976-12-16 | 1978-07-03 | Nippon Telegr & Teleph Corp <Ntt> | Variable amplitude equalizer |
-
1984
- 1984-10-09 JP JP15351284U patent/JPS6168507U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5040477A (en) * | 1973-08-07 | 1975-04-14 | ||
| JPS5374863A (en) * | 1976-12-16 | 1978-07-03 | Nippon Telegr & Teleph Corp <Ntt> | Variable amplitude equalizer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010135869A (en) * | 2008-12-02 | 2010-06-17 | Kyocera Mita Corp | Wiring substrate, image forming apparatus, and wiring method |
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