JPH0284405U - - Google Patents

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Publication number
JPH0284405U
JPH0284405U JP16492488U JP16492488U JPH0284405U JP H0284405 U JPH0284405 U JP H0284405U JP 16492488 U JP16492488 U JP 16492488U JP 16492488 U JP16492488 U JP 16492488U JP H0284405 U JPH0284405 U JP H0284405U
Authority
JP
Japan
Prior art keywords
circuit
phase delay
power distribution
duplexer
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16492488U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16492488U priority Critical patent/JPH0284405U/ja
Publication of JPH0284405U publication Critical patent/JPH0284405U/ja
Pending legal-status Critical Current

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  • Control Of Motors That Do Not Use Commutators (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例による分波器を示
す構成図、第2図はこの考案の他の実施例を示す
分波器の構成図、第3図は従来の分波器を示す構
成図である。 図において、21は電力分配回路、21a〜2
1cは電力分配回路21の入出力端子、22,3
0は位相遅延回路、22a〜22dは位相遅延回
路22の入出力端子、23,33はマジツクT回
路、23a〜23dはマジツクT回路23の入出
力端子、32は90゜ハイブリツドを示す。なお
、図中、同一符号は同一、または相当部分を示す
Fig. 1 is a block diagram showing a duplexer according to one embodiment of this invention, Fig. 2 is a block diagram of a duplexer showing another embodiment of this invention, and Fig. 3 shows a conventional duplexer. FIG. In the figure, 21 is a power distribution circuit, 21a to 2
1c is an input/output terminal of the power distribution circuit 21, 22, 3
0 is a phase delay circuit, 22a to 22d are input and output terminals of the phase delay circuit 22, 23 and 33 are magic T circuits, 23a to 23d are input and output terminals of the magic T circuit 23, and 32 is a 90° hybrid. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電力分配回路と位相遅延回路と電力合成回路を
備えたことを特徴とする分波器。
A duplexer characterized by being equipped with a power distribution circuit, a phase delay circuit, and a power combining circuit.
JP16492488U 1988-12-19 1988-12-19 Pending JPH0284405U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16492488U JPH0284405U (en) 1988-12-19 1988-12-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16492488U JPH0284405U (en) 1988-12-19 1988-12-19

Publications (1)

Publication Number Publication Date
JPH0284405U true JPH0284405U (en) 1990-06-29

Family

ID=31450951

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16492488U Pending JPH0284405U (en) 1988-12-19 1988-12-19

Country Status (1)

Country Link
JP (1) JPH0284405U (en)

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