JPS6338409U - - Google Patents
Info
- Publication number
- JPS6338409U JPS6338409U JP13039486U JP13039486U JPS6338409U JP S6338409 U JPS6338409 U JP S6338409U JP 13039486 U JP13039486 U JP 13039486U JP 13039486 U JP13039486 U JP 13039486U JP S6338409 U JPS6338409 U JP S6338409U
- Authority
- JP
- Japan
- Prior art keywords
- switch
- circuit
- turns
- load
- constant current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Amplifiers (AREA)
Description
第１図は本考案の一実施例のブロツク図である
。
１……電力増幅回路、２，３……負荷、４，５
……定電流回路、６……比較回路、７〜９……ス
イツチ。
FIG. 1 is a block diagram of one embodiment of the present invention. 1... Power amplifier circuit, 2, 3... Load, 4, 5
... Constant current circuit, 6 ... Comparison circuit, 7 to 9 ... Switch.
Claims (1)
第１の定電流回路と、前記第１の負荷に対応する
所定のインピーダンス値を有する第２の負荷に直
列に接続される第２の定電流回路と、前記第１及
び第２の負荷の電圧をそれぞれの入力とする比較
回路と、該比較回路の出力により開閉制御され前
記電力増幅回路に電源を供給する第１のスイツチ
と、前記第１のスイツチと互に逆相に動作し前記
比較回路の出力により開閉制御され前記第１及び
第２の定電流回路と前記比較回路に前記電源を供
給する第２のスイツチと、外部操作により導通状
態となり前記第２のスイツチを導通状態としかつ
所定の遅延時間をもつて前記第１のスイツチを導
通状態とする第３のスイツチとを含むことを特徴
とする電力増幅回路の保護回路。 a first constant current circuit connected in series to a first load of the power amplifier circuit; and a second constant current circuit connected in series to a second load having a predetermined impedance value corresponding to the first load. a current circuit, a comparator circuit that receives the voltages of the first and second loads as inputs, a first switch that is controlled to open and close by the output of the comparator circuit and supplies power to the power amplifier circuit; The second switch operates in opposite phase to the first switch and is controlled to open and close by the output of the comparison circuit, and is connected to the second switch that supplies the power to the first and second constant current circuits and the comparison circuit by an external operation. a third switch that turns on and turns on the second switch and turns on the first switch after a predetermined delay time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13039486U JPS6338409U (en) | 1986-08-26 | 1986-08-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13039486U JPS6338409U (en) | 1986-08-26 | 1986-08-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6338409U true JPS6338409U (en) | 1988-03-12 |
Family
ID=31027850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13039486U Pending JPS6338409U (en) | 1986-08-26 | 1986-08-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6338409U (en) |
-
1986
- 1986-08-26 JP JP13039486U patent/JPS6338409U/ja active Pending