JPS6244531U - - Google Patents

Info

Publication number
JPS6244531U
JPS6244531U JP13653385U JP13653385U JPS6244531U JP S6244531 U JPS6244531 U JP S6244531U JP 13653385 U JP13653385 U JP 13653385U JP 13653385 U JP13653385 U JP 13653385U JP S6244531 U JPS6244531 U JP S6244531U
Authority
JP
Japan
Prior art keywords
rams
digital
input
converter
digital switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13653385U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13653385U priority Critical patent/JPS6244531U/ja
Publication of JPS6244531U publication Critical patent/JPS6244531U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案を示すブロツク図、第2図、
第3図は、それぞれ実施例を示す要部の回路図、
第4図、第5図は、それぞれ従来例を示すブロツ
ク図である。 1,1……RAM、2,2……デイジ
タル切換器、3……A/Dコンバータ、4……D
/Aコンバータ、6……アドレス発生回路。
Fig. 1 is a block diagram showing the present invention, Fig. 2 is a block diagram showing the present invention;
FIG. 3 is a circuit diagram of the main part showing an example,
FIGS. 4 and 5 are block diagrams showing conventional examples, respectively. 1 1 , 1 2 ... RAM, 2 1 , 2 2 ... Digital switch, 3 ... A/D converter, 4 ... D
/A converter, 6...address generation circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 2つのRAM,を設け、一方のRAM,
の入・出力端に正動作のデイジタル切換器2
を、また、他方のRAM,1の入・出力端
に逆動作のデイジタル切換器2を接続し、入力
側のA/Dコンバータ3と出力側のD/Aコンバ
ータ4とをそれぞれそれらのデイジタル切換器2
,2を介して両RAM,へ接続し、それ
らのRAM,及びデイジタル切換器2,2
をコントロール回路5及びアドレス発生回路6
により適宜に制御するよう構成したことを特徴と
するデイジタル・デイレイ回路。
Two RAMs are provided, one RAM,
1 Direct-acting digital switch 2 at the input/output terminal of 1
In addition, a reverse-operating digital switch 22 is connected to the input/output terminals of the other RAM, 12 , and the A/D converter 3 on the input side and the D/A converter 4 on the output side are connected to each other. digital switch 2
1 and 2 to both RAMs through 2, and connect those RAMs and digital switches 2 1 and 2.
2 to the control circuit 5 and address generation circuit 6
A digital delay circuit characterized in that it is configured to be appropriately controlled by.
JP13653385U 1985-09-05 1985-09-05 Pending JPS6244531U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13653385U JPS6244531U (en) 1985-09-05 1985-09-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13653385U JPS6244531U (en) 1985-09-05 1985-09-05

Publications (1)

Publication Number Publication Date
JPS6244531U true JPS6244531U (en) 1987-03-18

Family

ID=31039735

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13653385U Pending JPS6244531U (en) 1985-09-05 1985-09-05

Country Status (1)

Country Link
JP (1) JPS6244531U (en)

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