JPS6372919U - - Google Patents
Info
- Publication number
- JPS6372919U JPS6372919U JP16771386U JP16771386U JPS6372919U JP S6372919 U JPS6372919 U JP S6372919U JP 16771386 U JP16771386 U JP 16771386U JP 16771386 U JP16771386 U JP 16771386U JP S6372919 U JPS6372919 U JP S6372919U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- switch
- terminal
- control terminal
- amplifier circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008054 signal transmission Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Amplifiers (AREA)
Description
第１図は本考案の、増幅回路の動作・非動作切
替回路の実施例を示す図である。
（主な参照番号）、１…電源、２…第１のスイ
ツチ、３…増幅回路の電源端子、４…増幅回路、
５…第２のスイツチ、６…第３のスイツチ、７…
第１のスイツチのドライバ、８…第３のスイツチ
のドライバ、９…論理積回路、１０…インバータ
回路、１１…遅延回路、１２…制御端子。
FIG. 1 is a diagram showing an embodiment of an operation/non-operation switching circuit for an amplifier circuit according to the present invention. (Main reference numbers), 1...Power supply, 2...First switch, 3...Power terminal of amplifier circuit, 4...Amplifier circuit,
5...Second switch, 6...Third switch, 7...
1st switch driver, 8... Third switch driver, 9... AND circuit, 10... Inverter circuit, 11... Delay circuit, 12... Control terminal.
Claims (1)
られ正論理で動作する第１のスイツチと上記増幅
回路の信号伝達ラインと接地間に設けられ負論理
で動作する第２のスイツチとを有し、上記第１と
第２のスイツチの制御端子は同一の制御端子に接
続する上記増幅回路の動作・非動作切替回路にお
いて、上記第２のスイツチの制御端子には上記電
源との間に直列に第３のスイツチを設け、上記同
一の制御端子にはインバータ回路と遅延回路を並
列に接続し、それぞれの出力端子を論理積回路の
入力端子に接続し、該論理積回路の出力端子を上
記第３のスイツチの制御端子に接続することを特
徴とする増幅回路の動作・非動作切替回路。 The first switch is provided in series between the power supply and the power supply terminal of the amplifier circuit and operates with positive logic, and the second switch is provided between the signal transmission line of the amplifier circuit and ground and operates with negative logic. The control terminals of the first and second switches are connected to the same control terminal in the operation/non-operation switching circuit of the amplifier circuit, and the control terminal of the second switch is connected in series with the power supply. An inverter circuit and a delay circuit are connected in parallel to the same control terminal, each output terminal is connected to the input terminal of an AND circuit, and the output terminal of the AND circuit is connected to the above control terminal. An operation/non-operation switching circuit for an amplifier circuit, characterized in that it is connected to a control terminal of a third switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16771386U JPS6372919U (en) | 1986-10-30 | 1986-10-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16771386U JPS6372919U (en) | 1986-10-30 | 1986-10-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6372919U true JPS6372919U (en) | 1988-05-16 |
Family
ID=31099900
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16771386U Pending JPS6372919U (en) | 1986-10-30 | 1986-10-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6372919U (en) |
-
1986
- 1986-10-30 JP JP16771386U patent/JPS6372919U/ja active Pending
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