JPS6283300U - - Google Patents
Info
- Publication number
- JPS6283300U JPS6283300U JP17635185U JP17635185U JPS6283300U JP S6283300 U JPS6283300 U JP S6283300U JP 17635185 U JP17635185 U JP 17635185U JP 17635185 U JP17635185 U JP 17635185U JP S6283300 U JPS6283300 U JP S6283300U
- Authority
- JP
- Japan
- Prior art keywords
- output terminal
- level
- memory cell
- data
- high level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Description
第１図は本考案の一実施例の回路図である。
１……メモリセル群、２……基準レベル発生回
路、３……切換回路、４……センス増幅器、１１
……信号データ、２１……基準データ、３３……
第１の出力端子、３４……第２の出力端子、４１
……正入力端子、４２……負入力端子。
FIG. 1 is a circuit diagram of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Memory cell group, 2...Reference level generation circuit, 3...Switching circuit, 4...Sense amplifier, 11
...Signal data, 21...Reference data, 33...
First output terminal, 34...Second output terminal, 41
...Positive input terminal, 42...Negative input terminal.
Claims (1)
メモリセルが高レベル又は低レベルの信号データ
を出力するメモリセル群と、前記高レベルと低ベ
レルとの中間レベルの基準データを出力する基準
レベル発生回路と、前記信号データと前記基準デ
ータとを入力としそれぞれの入力が予め設定する
ことにより切換え出力される第１及び第２の出力
端子を有する切換回路と、正入力端子が前記第１
の出力端子に接続され負入力端子が前記第２の出
力端子に接続されるセンス増幅器とを含むことを
特徴とする読出し専用メモリ。 A memory cell group in which each memory cell outputs high level or low level signal data according to preset data contents, and a reference level generation circuit that outputs reference data at an intermediate level between the high level and the low level. a switching circuit having first and second output terminals that receive the signal data and the reference data as inputs and are switched and outputted by setting the respective inputs in advance;
a sense amplifier connected to the output terminal of the second output terminal and having a negative input terminal connected to the second output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17635185U JPS6283300U (en) | 1985-11-15 | 1985-11-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17635185U JPS6283300U (en) | 1985-11-15 | 1985-11-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6283300U true JPS6283300U (en) | 1987-05-27 |
Family
ID=31116512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17635185U Pending JPS6283300U (en) | 1985-11-15 | 1985-11-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6283300U (en) |
-
1985
- 1985-11-15 JP JP17635185U patent/JPS6283300U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6283300U (en) | ||
| JPS583612U (en) | amplifier circuit | |
| JPS60111132U (en) | Digital data input circuit | |
| JPS6316713U (en) | ||
| JPH0353855U (en) | ||
| JPS6372919U (en) | ||
| JPS63100851U (en) | ||
| JPH0186000U (en) | ||
| JPS6178440U (en) | ||
| JPS58161313U (en) | High input impedance amplifier circuit | |
| JPS63138712U (en) | ||
| JPS58189619U (en) | level shift circuit | |
| JPH0178964U (en) | ||
| JPS61103969U (en) | ||
| JPS62105547U (en) | ||
| JPS6244531U (en) | ||
| JPH0328596U (en) | ||
| JPH02149412U (en) | ||
| JPS605153U (en) | solar cell module | |
| JPS60112821U (en) | Solar cell load starting device | |
| JPS591200U (en) | memory circuit | |
| JPS61107049U (en) | ||
| JPS63143904U (en) | ||
| JPS58131137U (en) | Solar cell circuit switching device | |
| JPH0397253U (en) |