JPH0178964U

JPH0178964U -

Info

Publication number: JPH0178964U
Application number: JP1987175680U
Authority: JP
Priority date: 1987-11-17
Filing date: 1987-11-17
Publication date: 1989-05-26

Description

[Brief explanation of the drawing]

第１図は、本考案の一実施例を示す構成図であ
る。１……ゲートアレーチツプ、２……入力バツフ
アブロツク、３……出力バツフアブロツク、４…
…内部セルアレー部、５……切換回路ブロツク、
６……信号線、７……スルー回路、ａ，ｂ……入
力バツフアブロツクの出力端子、ｃ，ｄ……出力
バツフアブロツクの入力端子。 FIG. 1 is a block diagram showing an embodiment of the present invention. 1...Gate array chip, 2...Input buffer block, 3...Output buffer block, 4...
...Internal cell array section, 5...Switching circuit block,
6... Signal line, 7... Through circuit, a, b... Output terminal of input buffer block, c, d... Input terminal of output buffer block.

Claims

[Scope of utility model registration request]

In a gate array circuit having a plurality of transistors as basic cells, a plurality of input buffer blocks are inserted between an internal circuit of the gate array and a plurality of external inputs, and a plurality of input buffer blocks are inserted between the internal circuit and a plurality of external outputs. Each of the output buffer blocks is provided with a through circuit terminal in addition to the terminal connected to the internal circuit, and the through circuit terminals of the plurality of input buffer blocks and the corresponding through circuit terminals of the plurality of output buffer blocks are provided. A gate array comprising: a plurality of through circuits that directly connect the plurality of input buffer blocks and the plurality of output buffer blocks; and means for separating the internal circuit inserted between the plurality of input buffer blocks and the plurality of output buffer blocks and switching to the through circuit. circuit.